Commit Graph
584 Commits
Author SHA1 Message Date
322a9cbb6e [BugFix] Isolate cross-compiler options per invocation (#2728)
* Keep cross-compiler options isolated per build

* Document cross-compiler option isolation

---------

Co-authored-by: Zheng Yu <17133261+cla7aye15I4nd@users.noreply.github.com>
Co-authored-by: SiriusNEO <chaofan@deepseek.com>
2026-07-22 19:00:59 +08:00
24a023c636 [BugFix][Transform] Never classify side-effecting binds as replayable (atomics re-executed at every use site since v0.1.11) (#2651)
* [Transform] Never classify side-effecting binds as replayable

IsReplayableScalarBind (introduced in #2245) decides whether a scalar
bind may be dissolved and its value re-evaluated at every use site
(IfStmtBinding, default-on) or replayed across pipeline stages
(PipelinePlanning, InjectSoftwarePipeline). The predicate checked the
dtype and read/write disjointness, but never the value's effect kind,
so a bind like

    pos = T.atomic_add(counter[0], 1, return_prev=True)

used at two sites (bound check + store index) was inlined into both use
sites, executing the atomic once per use site instead of exactly once
and silently corrupting compaction/histogram/top-k kernels since
v0.1.11. The atomic intrinsic is correctly registered kOpaque; its
pointer argument enters the expression through tvm_access_ptr, which
the access collector records as a read, so the write-disjointness check
passed and the bind was declared replayable.

Reject any bind whose value has SideEffect > kReadState, mirroring the
effect guard StmtSimplifier already applies to let inlining. Read-only
values remain replayable; read consistency is enforced by the existing
write-set disjointness check.

The shipped examples/deepseek_v32/topk_selector.py uses exactly this
pattern and is miscompiled on v0.1.11/v0.1.12; its test only printed
recall and could not fail, so it also gains a recall assertion.

Regression tests:
- transform: IfStmtBinding must keep a bind whose value is an atomic
  RMW returning the previous value.
- language (CUDA): compaction kernel using atomic_add(return_prev=True)
  must contain exactly one AtomicAddRet and produce a permutation with
  counter == N.

* [Transform] Validate scalar bind replay safety

Track access-pointer write masks during bind and pipeline analysis, and reject unsafe precomputed replay annotations during pipeline injection.

Add regressions for atomic target reads and side-effecting replay masks.

* Remove recall calculation from top-k selector

Removed recall calculation and assertion for top-k selection.

---------

Co-authored-by: LeiWang1999 <leiwang1999@outlook.com>
Co-authored-by: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
2026-07-22 17:43:01 +08:00
Lei Wang 052e6741c7 [TIR][Analyzer] Fix vectorized Select constraint handling (#2731)
[TIR] Handle broadcast Select conditions safely
2026-07-22 17:12:20 +08:00
sijieli2 9d819c3fc3 [BugFix] Fix MFMA DataType args causing compilation failure on ROCm (#2726)
Fix MFMA dtype args passed as DataType instead of str

When local_size is 1, compute_a_dtype/compute_b_dtype/compute_out_dtype
are assigned directly from self.a_dtype etc., which are tvm_ffi DataType
objects (a str subclass). The TVM FFI C++ layer dispatches DataType before
str in its type conversion, so these never get auto-converted to StringImm
(a PrimExpr). This causes MFMA GEMM compilation to fail on ROCm with:

  TypeError: Expected Array<ir.PrimExpr> but got Array[index 3: DataType]

The bug only triggers when local_size == 1 (e.g. float32 GEMM), because
when local_size > 1 the f-string produces a plain str.

Fix: convert dtype attrs to str() before building compute dtype strings.

Add test: testing/python/amd/test_mfma_dtype_str_bug.py
2026-07-22 16:28:11 +08:00
cc106fa2ad [Feature] Add lower-trace support for debugging & rebased (#2725)
* [feat] add lower-trace support for debugging

* [fix] address review: rebase, doc migration, lower_trace robustness

Address CodeRabbit + SiriusNEO review feedback on #2470:

Blocking (SiriusNEO):
- Rebase onto tile-ai/main (resolve docs/ + tilelang/__init__.py conflicts).
- Move IR Lower Trace doc from docs/tutorials/ to docs/tools/lower_trace.md
  (alongside pass_diff.md); add index entry and 'superseded' pointer on
  pass_diff.md; cross-link from the tutorial.

CodeRabbit Major:
- lower_trace/__init__.py: finally block uses active_exc pattern so a
  generate_html() failure can no longer mask the real lowering exception.
- lower_trace/html.py: sanitize rec.phase into DOM-safe IDs via _safe_id()
  before embedding in id="..." / selectors (avoids markup/JS breakage and
  local HTML injection from special characters).

CodeRabbit Minor:
- test_lower_trace.py: restore caller's TL_LOWER_TRACE* env after the guarded
  tilelang import instead of permanently clearing it.
- lower_trace/__init__.py: terminal mode prints a FAILED stanza (pass name,
  exception, pre-pass IR) before re-raising so the failing step is visible.
- lower_trace/core.py: _get_codegen_output_path() no longer auto-writes
  codegen.cpp in terminal-only mode (explicit override still honored).
- lower_trace/html.py: expandAll()/collapseCtx() null-guard the table lookup
  so a changed diff with no table fails safe.

Cleanup:
- Add docstrings to test helpers and tools.__getattr__ (coverage now 94%+).
- ruff check + format clean.

* [Docs] Add lower trace to tools sidebar

* [fix] route lower-trace env vars through tilelang.env

Register TL_LOWER_TRACE / TL_LOWER_TRACE_DIR as EnvVar in the central
Environment class with get_lower_trace_mode()/get_lower_trace_dir()
parsers, mirroring the existing TILELANG_PASS_DIFF convention, instead
of reading os.environ directly in the lower_trace module.

* [fix] simplify lower_trace lazy-import in tools __getattr__

Drop the redundant globals() cache assignment (import_module already
binds the submodule onto the parent package) and fix the docstring: the
module is imported lazily for cost, not to defer monkey-patch side
effects, which happen in enable(). Note why importlib is required over
"from . import" (the latter re-enters __getattr__ and recurses).

---------

Co-authored-by: caojian5 <caojian5@huawei.com>
Co-authored-by: SiriusNEO <chaofan@deepseek.com>
2026-07-22 16:27:01 +08:00
Zheng YuandZheng Yu bd5ca2f05a [BugFix] Preserve buffer element offsets in access pointers (#2727)
Preserve buffer offsets in access pointers

Co-authored-by: Zheng Yu <17133261+cla7aye15I4nd@users.noreply.github.com>
2026-07-22 15:42:39 +08:00
Liu Yunuo f8d8cd4b14 [BugFix] Use blockDim as workspace stride in batch AllReduce (#2621)
* fix: use blockDim as workspace stride in batch AllReduce

* add test
2026-07-21 18:46:14 +08:00
lianjinfeng2003 ac576c6356 [BugFix] Fix FP4 dequant symbolic exponent clamp (#2656)
* [BugFix] Fix FP4 dequant symbolic exponent clamp

* [BugFix] Align quantization regression
2026-07-21 18:23:49 +08:00
penguin_wwy 25c0a1556c [Transform] Replace CPU fallback thread placeholder with a constant-zero logical thread index (#2718)
* [BugFix] fix issue 2226

* Fix
2026-07-21 18:23:19 +08:00
Zheng YuandZheng Yu 8cfc90e026 [BugFix] Fix HIP predicated dword copy zero fill (#2721)
Fix HIP predicated dword copy zero fill

Co-authored-by: Zheng Yu <17133261+cla7aye15I4nd@users.noreply.github.com>
2026-07-21 17:52:19 +08:00
LyscoriaandSiriusNEO 88e007d4d7 [BugFix] Guard T.atomic_addx4 return type for sliced destinations (#2590)
[BugFix] Guard T.atomic_addx4 return type computation for sliced destinations

Co-authored-by: SiriusNEO <chaofan@deepseek.com>
2026-07-21 17:48:36 +08:00
Ruinan Li 656c287aff [BugFix] Fix wrong offset when scanning a non-zero-offset buffer sub-region (#2680)
fix: resolve issue 2536
2026-07-21 17:14:55 +08:00
xiaoyouPREG ce9ff0c1a7 [BugFix] Gate stochastic FP4/FP8 casts on sm_100a (#2691)
* [BugFix] Gate stochastic FP4/FP8 casts on sm_100a

* [BugFix] Move stochastic cast arch checks into CUDA templates
2026-07-21 14:18:27 +08:00
Liu Yunuo 39c5b4efe4 [BugFix] Correct IEEE math intrinsic names for fp64/fp16/bf16 (#2619)
* fix: correct IEEE math intrinsic names for fp64/fp16/bf16

* update test

* lint

* update
2026-07-21 14:04:42 +08:00
xiaoyouPREG ffeda9f394 [BugFix] Pack 32-lane 8-bit CUDA vectors correctly (#2701)
* [BugFix] Pack 32-lane 8-bit CUDA vectors correctly

* [Test] Avoid SM100-only store in int8 broadcast regression

* [BugFix] Move int8x32 packing into CUDA templates
2026-07-21 13:36:03 +08:00
wcxandLeiWang1999 8cdd4d62f3 [BugFix] Prevent partial 1-D TMA stores from bypassing bounds checks (#2716)
* [BugFix] Prevent partial 1-D TMA stores from bypassing bounds checks

Signed-off-by: UnsettingGalaxy <chenxuw641@gmail.com>

* [BugFix] Prevent partial 1-D TMA stores from bypassing bounds checks

Signed-off-by: UnsettingGalaxy <chenxuw641@gmail.com>

* [BugFix] Derive TMA copy bounds during selection

Remove buffer_oob from generic layout inference arguments and derive copy-region containment from the active analyzer in both inference and lowering. Use descriptor TMA for partial tiles and add rank-1 tail regression coverage.

---------

Signed-off-by: UnsettingGalaxy <chenxuw641@gmail.com>
Co-authored-by: LeiWang1999 <leiwang1999@outlook.com>
2026-07-20 19:42:49 +08:00
FtoandYu Cheng 46f3b31a53 [BugFix][WS] Fix pipeline replacement under persistent T.serial (#2674)
* [BugFix][WS] Fix pipeline replacement under persistent T.serial

* [BugFix][WS] Address review feedback

* [BugFix][WS] Address review feedback

* [BugFix][WS] Restrict stage replacement to MVB indices

* [BugFix][WS] Address coderabbit feedback

---------

Co-authored-by: Yu Cheng <yu.cheng@pku.edu.cn>
2026-07-20 18:53:13 +08:00
Xiangwen Wang 4433981c99 [Enhancement] Add local buffer reduction lowering (#2693)
* Add local buffer reduction lowering

* Minor fix

* Simplify
2026-07-20 17:49:14 +08:00
morluto 335afcf8a3 [BugFix] Decode FP8 E4M3 special encodings correctly (#2710) 2026-07-20 14:06:46 +08:00
morluto 134f9c2e8a [BugFix] Implement atomic load and store for HIP (#2711) 2026-07-20 13:36:00 +08:00
morluto bfe126d1ce [BugFix] Support return_prev for HIP vector atomic add (#2712) 2026-07-20 13:32:26 +08:00
Liu Yunuo 0c7f14c3f9 [BugFix] Fix WGMMA C-store layout for multiple warpgroups along M (#2663)
* fix wgmma store layout

* fix wgmma_sp the same way, update testing requirements
2026-07-17 17:09:22 +08:00
Lyscoria 4aea435ba7 [BugFix] Reject unsafe non-warp-multiple partial thread sync (#2679)
* Add clear LOG(FATAL) message

* Add tests

* Use target warp size for partial thread sync
2026-07-17 15:33:21 +08:00
xiaoyouPREG 9754ac4471 [BugFix] Preserve bf16 NaN and Inf during RNE packing (#2690) 2026-07-17 13:50:39 +08:00
Yuanyuan Zhao 61f968b6c5 [BugFix] Track GEMM accumulator writes in warp-specialization liveness collector (#2685)
* [BugFix] Track GEMM accumulator writes in warp-specialization liveness collector

* [BugFix] Track scale-factor regions and region extents in gemm liveness
2026-07-17 11:25:19 +08:00
penguin_wwy 4a5cf099fb [Feature] Add compiler pass timing profiling (#2622) 2026-07-16 21:36:07 +08:00
Yuanyuan ZhaoandLeiWang1999 9ff4ef8d43 [BugFix] Respect safe value in tile copy OOB (#2636)
* [BugFix] Respect safe value in tile copy OOB

* [Style] Apply ruff format to copy test

* [BugFix] Pass copy safe values as lowering map

* [BugFix] Resolve copy safe values during parsing

* [Refactor] Move copy safe-value parsing to tile op handler

* [Refactor] Simplify ParseOperator default annotations

* Add ICHECK assertion for node

---------

Co-authored-by: LeiWang1999 <leiwang1999@outlook.com>
2026-07-16 18:34:42 +08:00
Lyscoria 31755e7138 [BugFix] Support runtime-dependent vector negative indices (#2654) 2026-07-16 18:30:46 +08:00
Lei Wang 66837430ab [JIT][TVM-FFI] Reuse executable across kernel launches (#2686)
[JIT] Reuse TVM FFI executable across launches
2026-07-16 17:54:03 +08:00
Chennes 4f442a395e [BugFix] Reject invalid atomic load and store memory orders (#2666)
T.atomic_load and T.atomic_store previously accepted every order in the shared memory-order map, including operation-illegal combinations that trigger device-side assertions in libcu++.

Validate memory orders against operation-specific allow lists before lowering, report invalid values with a frontend ValueError, and update the documentation and regression coverage accordingly.

Fixes #2574
2026-07-16 14:22:20 +08:00
Xuyang LiandLeiWang1999 c5e5307621 [BugFix] Return previous value for scalar atomic_min/atomic_max (#2672)
* [BugFix] Return previous value for atomic min/max/add (scalar + vectorized)

`atomic_min`/`atomic_max` (scalar) and `atomic_addx2`/`atomic_addx4`
(vectorized) typed their call with a non-void return under
`return_prev=True` but always selected the void `*_elem_op`, so codegen
emitted an empty binding (`prev = ;`) and nvcc failed.

Select the `*_ret_elem_op` variant under `return_prev`, as `atomic_add`
already does:
- min/max: the ret ops, codegen handlers, and device templates
  (AtomicMaxRet/AtomicMinRet) already existed.
- addx2/addx4 (float32): register the ret ops (builtin.cc/.h) and add
  codegen handlers emitting AtomicAddx2Ret/AtomicAddx4Ret (already in
  the device headers) as expressions; the return is typed as the packed
  2-/4-lane vector so the store matches.
- addx2 (fp16/bf16): the ret store LHS is `uint1`; codegen wraps the
  half2/bf162 result with `tl::to_uint1`.
- addx4 (fp16/bf16): add AtomicAddx4Ret(half_t*)/(bfloat16_t*) device
  overloads that run two AtomicAddx2Ret halves and return them packed as
  uint2 (a fp16x4 is stored as uint2).

The 16-bit x4 path is per-pair atomic (two half2 atomics), not
whole-quad single-atomic -- hardware has no vector atomic wider than
`.f16x2` for 16-bit types. This matches the existing fp32-x4 scalar
fallback, and the docstring only promises "quad-width atomic addition".
Adds tests across scalar/x2/x4 and float32/fp16/bf16.

Fixes #2667

* minor fix for missing conditiions

---------

Co-authored-by: LeiWang1999 <leiwang1999@outlook.com>
2026-07-16 13:48:57 +08:00
Xuyang Li d36ec37c59 [BugFix] Support T.infinity for float8_e5m2 (#2671)
`T.infinity` aborted with an internal `LOG(FATAL)` ("Cannot decide
infinity for type float8_e5m2") because `infinity_op` had no fp8 branch.
e5m2 is the only fp8 format with a representable inf, so add a branch
returning +inf, and emit it in codegen via its bit pattern
(`::bitcast(0x7c)`, mirroring the tfloat32 path) since inf/NaN cannot be
spelled as a float literal for the fp8 constructor. Other fp8 formats
(e4m3*, e3m4, e8m0, finite fnuz incl. e5m2fnuz) have no inf and keep the
fatal. Adds e5m2 to the infinity test.
2026-07-15 17:37:20 +08:00
Lei Wang 3af87b7fb6 [TIR][Transform] Fix flat Bind modeling in parallel race checks (#2665)
[TIR] Fix flat Bind modeling in parallel race checks
2026-07-15 10:55:23 +08:00
Lei Wang 70548a1707 [BugFix][CUDA][HIP] Correct packed shared memory allocation sizes (#2660)
Fix packed shared memory allocation sizes
2026-07-14 16:11:22 +08:00
penguin_wwy effebb6bf0 [BugFix] Fix segfault when tunable params default to None (#2657) 2026-07-14 14:11:20 +08:00
Lei Wang 1ac5a01a4e [TIR][Runtime] Enforce host-evaluable assumptions at runtime (#2655)
* Add runtime checks for host-evaluable assumptions

* Preserve nullable buffer semantics for assume checks

* Rename assume runtime-check marker
2026-07-14 12:24:26 +08:00
Da1L8-Xanddaniu.ld 6ed02aee47 [Autotune] Support per-config pass_configs in autotuning (#2496)
* feat(autotuner): support per-config pass_configs with code deduplication

- Extract _merge_pass_configs_into_compile_args helper to deduplicate
  pass_configs merge logic across grouped_compile.py and tuner.py
- Replace json.dumps uniformity check with direct equality comparison
- Extract _make_jit_compile_func factory to unify lazy/eager jit_compile
- Fix decorator-mode cache isolation: use compile() directly when
  per_config_pass_configs is present to avoid JIT cache key collision
- Add example and test for per-config pass_configs tuning

* docs: add docstrings to meet coverage threshold

* refactor(autotuner): move pass_configs resolution to tuner so grouped compile handles uniform configs

* fix(autotuner): define _PASS_CONFIGS_KEY constant and fix jit_compile race condition

- Replace all magic string "__pass_configs__" with _PASS_CONFIGS_KEY constant
- Move _pass_configs_lock to cover both branches in jit_compile to prevent
  concurrent reads of temporarily mutated pass_configs

* refactor(autotuner): introduce type aliases for compile-unit bookkeeping

- Add ConfigArg, UnitItem, UnitResult, CompileUnit type aliases
- Replace all long tuple type annotations with aliases
- Expand example configs to include num_stages=[1,2] and enable_grouped_compile

---------

Co-authored-by: daniu.ld <daniu.ld@alibaba-inc.com>
2026-07-13 22:24:19 +08:00
禾可 207f3a75f2 [BugFix] Reject non-positive thread extents in T.Kernel (#2653)
* [BugFix] Reject non-positive thread extents in T.Kernel

`_normalize_threads` passed its argument straight through, so a non-positive
extent such as `T.Kernel(1, threads=-1)` compiled and launched cleanly while
writing nothing. Validate the normalized extents and raise instead.

Concrete integer extents only, so symbolic extents keep working.

Fixes #2633.

Signed-off-by: 林晨 (Leo Cheng) <leo-cheng@vip.qq.com>

* [BugFix] Document _normalize_threads contract

Signed-off-by: 林晨 (Leo Cheng) <leo-cheng@vip.qq.com>

---------

Signed-off-by: 林晨 (Leo Cheng) <leo-cheng@vip.qq.com>
2026-07-13 17:29:01 +08:00
Chennes c8c49d5025 [BugFix] Reject invalid dtypes in T.dp4a (#2652)
T.dp4a previously accepted arbitrary buffer dtypes and passed them to backend DP4A implementations, which could silently reinterpret the operand bytes and produce incorrect results.

Require both inputs to use int8 and the accumulator to use int32. Add regression coverage for valid Buffer and BufferLoad forms and for invalid input and accumulator dtypes.

Fixes #2600
2026-07-13 17:13:24 +08:00
Zihao WangandLeiWang1999 5dfa0f5d6e [BugFix] Fix grouped reduce_sum over-counts on straddle layout (#2424)
* Fix reduce ownership for straddled layouts

* Guard reduce thread ownership projection

---------

Co-authored-by: LeiWang1999 <leiwang1999@outlook.com>
2026-07-13 11:50:03 +08:00
Yongqi Zhuo 1e07514959 [CUDA] Support fp32x2 ops as reducers (#2637) 2026-07-12 21:47:32 +08:00
Tong WUandLeiWang1999 228c7c0486 [Feature] Support iket profiler for CUDA backend (#2515)
* Add experimental IKET CUDA backend hooks

* Keep IKET APIs under namespace

* Use real Perfetto screenshot for IKET example

* Show IKET events in Perfetto timeline screenshot

* Add IKET validation overhead example

* Remove IKET validation overhead example

* Fix IKET lint issues

* Move IKET integration to CUDA tools

* Add tools documentation and fix workflow regressions

---------

Co-authored-by: LeiWang1999 <leiwang1999@outlook.com>
2026-07-12 20:03:30 +08:00
Yuanyuan Zhao bd76473830 [BugFix] Preserve guard identity in LoopUnswitching (#2585) 2026-07-11 14:29:20 +08:00
Lei Wang 250c1fc9ed [TIR][Codegen] Preserve decoupled cast buffer scope (#2545)
Preserve lexical scope for decoupled casts
2026-07-08 14:36:12 +08:00
Lei Wang 8533d2a987 [Language][Scheduler] Expose scalar tile scheduler state (#2553)
Expose scalar tile scheduler state
2026-07-08 14:34:55 +08:00
Lei Wang efce11ed25 [CUDA][Codegen] Keep RNG state in kernel scope (#2540)
Fix CUDA RNG state scope
2026-07-07 14:41:03 +08:00
Lei Wang 0d97af896e [CUDA][Cache] Include compile options in binary cache key (#2532)
* Include CUDA compile options in binary cache key

* enhance
2026-07-07 00:09:22 +08:00
Shuyi LinandClaude 16af6f805e [Feature][Tool] Add pass_visualizer: structure-tree pass browser (#2449)
* [Feature] Add pass_visualizer: structure-tree pass browser

Add an interactive, pass-by-pass IR structure-tree visualizer under
tilelang/utils/pass_visualizer. It complements the existing text-level
pass_diff tool by rendering the SBlock structure tree and expanding tile
ops by field name, with per-class operator highlighting (tile op / sync /
lowered hardware intrinsic) across the CUDA lowering prologue.

Includes a CLI entry point, an example gemm_relu kernel, a pytest suite,
and a docs section contrasting it with pass_diff.

Co-Authored-By: Claude <noreply@anthropic.com>

* Move pass_visualizer to tilelang/tools and fix prologue + review issues

- Move package from tilelang/utils to tilelang/tools per review
- Add missing MaterializeKernelLaunch pass (fixes CUDA CI modulo-by-zero)
- Escape "</" in embedded JSON to prevent <script> injection in HTML report
- Use explicit utf-8 encoding for source/output file I/O
- Guard _fmt_shape against symbolic shapes and validate module spec

Co-Authored-By: Claude <noreply@anthropic.com>

---------

Co-authored-by: Claude <noreply@anthropic.com>
2026-07-06 15:39:54 +08:00
penguin_wwy af2483f904 [BugFix] Fix llvm auto backend resolution (#2519) 2026-07-06 10:55:13 +08:00
Lei Wang 14fc963089 [Transform][Layout] Avoid thread-indexed replicated fragment readback (#2514)
Avoid thread-indexed replicated fragment readback
2026-07-03 14:52:24 +08:00