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copilot/feature-atomic-ops-shared-memory

copilot/fix-github-actions-job

dev

feat/tileir-support

fix/tma-unaligned-box-offset

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0.1.6

0.1.7.post2

v0.0.1

v0.1.0

v0.1.1

v0.1.10

v0.1.11

v0.1.12

v0.1.13

v0.1.14

v0.1.15

v0.1.2

v0.1.2.post1

v0.1.3

v0.1.4

v0.1.5

v0.1.6.post1

v0.1.6.post2

v0.1.7

v0.1.7.post1

v0.1.7.post2

v0.1.7.post3

v0.1.8

v0.1.9

Mono Color

• 994b44eca1 [Ascend] Add PTO backend for Ascend950 (#3310) main 6 people 2026-09-30 12:08:45 +08:00
• a35f8ddf45 [Release] Bump version into 0.1.15 (#3309) v0.1.15 Lei Wang 2026-09-30 07:31:57 +08:00
• e5a02f9aab [Public Release 9/30] Introduce Ascend 950 backend (#3308) +1727 people 2026-09-30 07:31:01 +08:00
• 8c484d7a27 [Build][Windows] Restore ccache hits for clang-cl wheel builds (#3305) Lei Wang 2026-09-29 18:58:13 +08:00
• 16a524176b [BugFix] Eliminate unused bindings in Simplify (#3293) Xiangwen WangandLeiWang1999 2026-09-29 14:12:12 +08:00
• ff799ed886 [Fix][TVM] Update TVM to preserve dynamic reduction tail guards (#3294) Lei Wang 2026-09-28 19:09:51 +08:00
• fb5a47aed2 [Build] Optimize default single-config builds (#3191) KellyFrog 2026-09-28 15:28:59 +08:00
• 74369d9e34 [CUDA] Reject conflicting SM120 scale fragment layouts (#3284) Lei Wang 2026-09-27 19:18:17 +08:00
• 7a5f446fde [CUDA] Support SM120 block-scaled GEMM fragments and odd warp atom grids (#3257) SepcntandLeiWang1999 2026-09-26 23:39:54 +08:00
• 356f309621 [CUDA] Keep FP8 vector copies packed (#3276) Lei Wang 2026-09-25 14:17:22 +08:00
• 134ade7d81 [Transform][CUDA] Fix async copy lowering with partitioned layouts (#3278) Lei Wang 2026-09-24 23:22:35 +08:00
• 7763c88000 [BugFix] Fix parallel loop lowering with let inlining disabled (#3269) penguin_wwy 2026-09-24 17:45:28 +08:00
• ea42ce56f4 [Fix] Reject unsupported reduction NaN propagation dtypes (#3273) Ziming WangandLeiWang1999 2026-09-24 17:03:43 +08:00
• 73c8fa0579 [BugFix][Language] Lower NaN-propagating clamp through device templates (#3205) 小云andLeiWang1999 2026-09-24 13:44:21 +08:00
• e4e14156d7 [BugFix] Bind loop targets independently of mutable scalar variables (#3232) SepcntandLeiWang1999 2026-09-23 13:54:33 +08:00
• 227515d27b [Fix]Clamp T.copy/T.async_copy coalesced_width to achievable vector size instead of LOG(FATAL) (#3246) edragainandLeiWang1999 2026-09-23 11:52:40 +08:00
• 8cf0e7eff4 [CUDA] Fuse exact FP4 to FP8 conversion through FP32 (#3204) Ziming WangandLeiWang1999 2026-09-22 19:36:44 +08:00
• 68656981e6 [Merge] Update TileIR branch with current upstream main feat/tileir-support Zhengyi Zhang 2026-09-21 22:57:55 -07:00
• 40c6238647 [TileIR] Mark explicit CUDA instruction examples as expected failures Zhengyi Zhang 2026-09-18 08:57:40 +00:00
• f09dd4aeff [TileIR] Match known example failures by exact test name Zhengyi Zhang 2026-09-18 08:43:07 +00:00
• dada9250a8 [TileIR] Fix packed tensor dispatch and persistent loop state Zhengyi Zhang 2026-09-18 08:17:54 +00:00
• fd98bd641d [TileIR] Keep conditional load tokens within their regions Zhengyi Zhang 2026-09-18 07:41:31 +00:00
• b1b3a8e1e6 [TileIR] Preserve empty launch hint compatibility Zhengyi Zhang 2026-09-18 07:25:08 +00:00
• 609354962d [TileIR] Align dialect hints and GEMM lowering with main Zhengyi Zhang 2026-09-18 06:49:15 +00:00
• e903fcdd2c [Merge] Sync TileIR backend with upstream main Zhengyi Zhang 2026-09-21 22:56:54 -07:00
• 6679f91387 [BugFix][JIT] Allocate a dynamic-shape output that precedes its sizing input (#3207) 小云andxy200303 2026-09-22 01:42:26 +08:00
• b7bfe82807 [BugFix][CUDA] Lower a kernel-body assert to a device-legal check (#3206) 小云andLeiWang1999 2026-09-22 01:41:42 +08:00
• 261a9e4bb1 [NVRTC] Fix warp reduction compilation (#3260) Sepcnt 2026-09-22 00:15:59 +08:00
• 1b908fc0eb [BugFix] Reject non-power-of-two AllReduce thread strides (#3266) Lei Wang 2026-09-21 21:18:16 +08:00
• 195b6ebbf3 [Frontend] Remove warnings for immutable variable rebinding (#3262) Xiangwen Wang 2026-09-21 16:23:19 +08:00
• 6ba187e20d [Frontend] Support Python iterables and comprehensions (#3230) SepcntandLeiWang1999 2026-09-21 13:28:09 +08:00
• eab74a4ae5 [ROCm] Add GLM-5.3 k-pool Top-K transform (#3254) andyluo7 2026-09-20 02:06:42 -07:00
• 054bcf1de3 [Testing] Drop duplicated codegen-smoke tests; fix fastmath self-comparison assertions (#3252) penguin_wwy 2026-09-20 01:44:09 +08:00
• 901f941c0d [Metal] Support 32-bit integer atomic add (#3211) Anders 2026-09-19 05:55:13 -07:00
• 4bc6c32a63 [BugFix][CUDA] Only emit 256-bit global load/store on SM100+ targets (#3248) penguin_wwy 2026-09-19 13:15:58 +08:00
• 48cd23e181 [ROCm] Run portable example validation in CI (#3165) andyluo7 2026-09-18 10:56:44 -07:00
• efe9654bf4 [BugFix] Restore symbolic loop-layout injectivity proof; reject layouts on symbolic shared tiles (#3233) 3 people 2026-09-18 14:56:02 +08:00
• 3de44fcbc0 [Examples][TileIR] Cover Pro schedule and clarify stride limits Zhengyi Zhang 2026-09-18 06:24:15 +00:00
• eeb0956963 Update sparse_attn_fwd_tileir.py Baihui Jin 2026-09-17 21:16:26 -07:00
• 5f12eafe31 Update sparse_attn_fwd_tileir.py Baihui Jin 2026-09-17 21:10:50 -07:00
• e40e09e3e6 [JIT] Add missing uint64 argument type mappings (#3229) Sepcnt 2026-09-17 17:57:55 +08:00
• d4787e9bb1 [Do not review][Op][Language][CUDA] Add common block-scaled GEMM semantics and backend dispatch (#3237) Lei Wang 2026-09-17 17:42:45 +08:00
• 0dc1d072fb [Examples][TileIR] Document the Pro 32K stride limit Baihui Jin 2026-09-17 02:27:08 -07:00
• 19b530117d [Examples][TileIR] Document and test tuned Flash attention schedule Baihui Jin 2026-09-17 01:35:50 -07:00
• 563c44f797 [Examples][TileIR] Add tuned DeepSeek V4 sparse attention Baihui Jin 2026-09-17 01:01:17 -07:00
• e688a439a8 [Transform][CUDA] Plan atomic vector widths from destination addresses (#3238) Lei Wang 2026-09-17 00:14:35 +08:00
• c6ece483b1 [BugFix][Vectorize] Keep atomic_add scalar for invariant/non-contiguous destinations (#3219) AlfredandLeiWang1999 2026-09-16 19:29:34 +08:00
• 80299bf1c5 [CPU] Import the CPU dialect in CPU tests (#3236) penguin_wwyandLeiWang1999 2026-09-16 17:22:08 +08:00
• db5584f2d3 [Profiler] Split timing helpers and add wall-clock benchmarking (#3234) Chaofan Lin 2026-09-16 14:10:12 +08:00
• e350730319 [Example] FP8 sparse MLA forward for DeepSeek V3.2 on Hopper (#3224) xuebozhang525-alt 2026-09-16 12:59:27 +08:00
• 96815790f5 [CUDA] Fix boolean bitwise negation codegen (#3228) SepcntandКарим 2026-09-16 12:21:05 +08:00
• 4c9cf5c7ea [Runtime] Fix library loading for symlink installs (#3227) Sepcnt 2026-09-15 12:09:34 +08:00
• 030556de97 [BugFix][Metal] Respect GEMM buffer region offsets (#3209) Anders 2026-09-14 02:54:44 -07:00
• 825bfd7ead [Transform] Restore bind-before-use order when merging constraint sets (#3221) Lei Wang 2026-09-14 13:50:54 +08:00
• 0e5c293c70 [Refactor][JIT] Replace callee-allocated-output target sniffing with a backend capability flag (#3218) Lei Wang 2026-09-12 22:07:05 +08:00
• 5e149e3167 [Language] Restore deprecated T.symbolic alias (#3216) Lei Wang 2026-09-12 15:56:45 +08:00
• dae277aebb [BugFix][CPU] Legalize BF16 arithmetic in the CPU pipeline (#3201) Anders 2026-09-12 00:08:47 -07:00
• 66c003c3e7 [Refactor][Language] Move backend-specific op hints into their owning dialects (#3203) Lei Wang 2026-09-12 01:52:03 +08:00
• c629fe5e61 [Cleanup][Language] Remove dead T.Pipelined(sync/group) and T.gemm_sp(k_pack) parameters (#3202) Lei Wang 2026-09-11 17:46:21 +08:00
• 85fd8fc2d3 [Refactor][Language] Make T.Kernel target-neutral with dialect-owned launch annotations (#3186) Lei Wang 2026-09-10 17:33:50 +08:00
• a72809bff2 [CI] Build pinned TileIR bindings in a dedicated job Zhengyi Zhang 2026-09-10 01:51:59 -07:00
• cdd110fff3 [BugFix][TileIR] Support 16-bit integer temporary buffers Zhengyi Zhang 2026-09-10 01:51:54 -07:00
• ffa747eb0a [BugFix][TileIR] Preserve shared pre-lowering semantic checks Zhengyi Zhang 2026-09-10 01:51:49 -07:00
• 8c63439cc8 [BugFix][TileIR] Preserve view capacity and shaped loop state Baihui JinandZhengyi Zhang 2026-09-10 01:10:01 -07:00
• 4956b5a174 [TileIR] Support CUDA Tile 13.4 and restore example coverage Zhengyi Zhang 2026-09-10 01:03:48 -07:00
• a3641cf463 [BugFix][TileIR] Align semantic region and cache contracts Zhengyi Zhang 2026-09-09 19:58:37 -07:00
• 2a871cbe10 [TileIR] Guard unsafe repeated-launch kernels Zhengyi Zhang 2026-07-17 07:50:34 +00:00
• a10a916207 [Doc][TileIR] Add a tuning guide and runnable example Zhengyi Zhang 2026-07-17 05:01:24 +00:00
• e1fc15e414 [Refactor][TileIR] Align backend code style Zhengyi Zhang 2026-07-15 08:03:44 +00:00
• 597e21f4bb [TileIR] Enforce examples and CI contracts Zhengyi Zhang 2026-07-15 06:59:54 +00:00
• 715d87755d [TileIR] Document and package the toolchain contract Zhengyi Zhang 2026-07-15 06:59:49 +00:00
• ac60e2cd9f [TileIR] Add JIT and autotuning test coverage Zhengyi Zhang 2026-07-15 06:59:41 +00:00
• 8a2239c881 [TileIR] Add runtime and numerical test coverage Zhengyi Zhang 2026-07-15 06:59:36 +00:00
• 4737d768a4 [TileIR] Add compiler and lowering test coverage Zhengyi Zhang 2026-07-15 06:59:29 +00:00
• 26133f50ef [TileIR] Integrate JIT runtime cache and autotuning Zhengyi Zhang 2026-07-15 06:59:18 +00:00
• c0a75733ef [TileIR] Integrate frontend operations and CUDA codegen Zhengyi Zhang 2026-07-15 06:59:12 +00:00
• 23f14cb5e1 [TileIR] Add typed backend compiler core Zhengyi Zhang 2026-07-15 06:59:05 +00:00
• 752312c2a9 [Refactor] [CUDA] Rename AutoSchedule to AutoWarpSpecialization (#3185) Yongqi Zhuo 2026-09-09 16:26:03 +08:00
• 3501787f4b [CI] Fail the perf bot on a regression instead of only reporting it (#3182) cklxx 2026-09-09 13:09:58 +08:00
• bd8e77dac1 [CI] [pre-commit.ci] autoupdate (#3181) pre-commit-ci[bot] 2026-09-08 03:58:25 +08:00
• 7525499330 [CUDA][Cache] Publish immutable binary cache directories (#3177) Lei WangandClaude Fable 5 2026-09-08 02:46:47 +08:00
• 62bba8d20d [Transform] Add snapshot mode to FreshenMutableReads (#3174) Lei Wang 2026-09-07 16:03:30 +08:00
• e0e21ce646 [Layout] Consider scalar reducer plans in register-count search (#3171) Lei Wang 2026-09-07 13:32:20 +08:00
• c63a2e7050 [BugFix][Transform] Keep shared FP32 atomics scalar on SM90 (#3129) Ziming Wang 2026-09-06 20:37:13 -07:00
• 11ec2397fe [Cache] Store cached kernel params as JSON instead of cloudpickle (#3143) Rishabh Sinha 2026-09-06 01:06:20 -07:00
• 479b9f6bd0 [ROCm] Support wave64 Hadamard transforms (#3154) andyluo7 2026-09-05 23:14:25 -07:00
• 1a1df62e94 [Language] Remove deprecated T.symbolic alias (#3122) Chaofan LinandLeiWang1999 2026-09-04 23:56:52 +08:00
• d0ff9b578b [CUDA] Resolve symlinked nvcc before deriving CUDA_HOME (#2839) morluto 2026-09-04 19:17:57 +08:00
• ccb48c39fb [Feature] [CUDA] Role-based automatic warp specialization (#3059) Yongqi ZhuoandLeiWang1999 2026-09-04 17:22:32 +08:00
• c9192939ce [CUDA] Add async-proxy fences for sparse MMA intrinsics (#3139) Ziming Wang 2026-09-03 23:50:02 -07:00
• bdbf32acf9 [Bugfix][Language] Support unary plus on PrimExpr in the eager frontend (#3141) Rishabh Sinha 2026-09-03 23:49:09 -07:00
• c24ce05b03 [Doc] Document pip installation on AMD GPUs (ROCm) (#3168) Lei Wang 2026-09-04 14:48:02 +08:00
• aab96fe918 [CI] Validate built wheels on GPU runners in the Dist workflow (#3167) Lei Wang 2026-09-04 14:34:37 +08:00
• 77abbde5f1 [BugFix][ROCm] Resolve hipcc robustly instead of trusting bare PATH lookup (#3166) Lei Wang 2026-09-04 13:47:46 +08:00
• 0f13a2c548 [CUDA] Add 16-bit hpow and hfmod bridges (#3163) Chennes 2026-09-03 23:14:49 +08:00
• e07bd1d009 [Refactor][CUDA] Replace per-lane-count vector constructors with variadic packers (#3158) Lei Wang 2026-09-03 23:01:35 +08:00
• 45ea657e88 [Language] Cache dtype.as_torch and demote storage-dtype fallback logs to debug (#3160) Lei Wang 2026-09-03 17:09:52 +08:00
• a256c89470 [Misc] Expose .agents skills to Claude Code via .claude/skills symlinks (#3161) Lei Wang 2026-09-03 16:25:57 +08:00
• 73bbff582d [BugFix][Carver] Compare sm_version numerically in plan_rasterization (#3144) Mocus Zhang 2026-09-03 17:51:32 +10:00
• 021592f4e5 [Example] Fix hadamard reference precision on TF32 and add pytest entry for CI (#3126) GaoXC-zhichu 2026-09-03 13:44:36 +08:00