KellyFrog 7bfaf7dde0 [Enhancement] Disable data race check by default, opt-in via env var (#2851) ...

The VerifyParallelLoop data race check can report false positives on
shared buffer stores whose per-thread addresses cannot be proven
distinct (e.g. indices loaded from fragments). Disable it by default;
users can opt in via the TILELANG_ENABLE_DATA_RACE_CHECK environment
variable or by explicitly setting the tl.disable_data_race_check pass
config to False.

2026-08-03 16:55:27 +08:00

..

test_nullable_buffer_params.py

[BugFix] ArgBinder: relax shared-shape binding for unused nullable buffers (#1870)

2026-02-24 11:43:55 +08:00

test_readonly_param_const_codegen.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_transform_cluster_planning.py

[Backend] Add target detector/normalizer registeration and merge ExecutionBackend into backend module (#2323)

2026-06-09 00:35:07 +08:00

test_tilelang_transform_config_index_bitwidth.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_transform_decouple_type_cast.py

[TIR][Codegen] Preserve decoupled cast buffer scope (#2545)

2026-07-08 14:36:12 +08:00

test_tilelang_transform_disable_memory_reuse.py

[CUDA][IR] Preserve dynamic shared memory aliases (#2240)

2026-05-21 18:12:58 +08:00

test_tilelang_transform_flatten_buffer.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_fuse_mbarrier_arrive_expect_tx.py

[Backend] Add target detector/normalizer registeration and merge ExecutionBackend into backend module (#2323)

2026-06-09 00:35:07 +08:00

test_tilelang_transform_hoist_broadcast_values.py

[Backend] Add target detector/normalizer registeration and merge ExecutionBackend into backend module (#2323)

2026-06-09 00:35:07 +08:00

test_tilelang_transform_if_stmt_binding.py

[BugFix] Preserve if condition evaluation during fan-out (#2764)

2026-07-25 14:30:13 +08:00

test_tilelang_transform_im2col_fallback.py

[Example] Migrate eligible examples to eager style (#2010)

2026-05-21 20:27:06 +08:00

test_tilelang_transform_inject_fence_proxy.py

[CUDA] Reduce template include overhead (#2474)

2026-07-01 16:53:07 +08:00

test_tilelang_transform_inject_set_max_nreg.py

[Transform] Place auto WS producers in first warp group (#2315)

2026-06-04 14:47:52 +08:00

test_tilelang_transform_Inject_software_pipeline.py

[BugFix][Transform] Never classify side-effecting binds as replayable (atomics re-executed at every use site since v0.1.11) (#2651)

2026-07-22 17:43:01 +08:00

test_tilelang_transform_inject_tcgen05_fence.py

[CUDA] Pack logical TMEM buffers into shared tcgen05.alloc arenas (#2831)

2026-08-03 13:53:12 +08:00

test_tilelang_transform_layout_inference.py

[BugFix] Fix LayoutInference divide-by-zero on non-power-of-two broadcast (#2469)

2026-07-03 14:30:26 +08:00

test_tilelang_transform_legalize_negative_index.py

[BugFix] Support runtime-dependent vector negative indices (#2654)

2026-07-16 18:30:46 +08:00

test_tilelang_transform_legalize_safe_memory_access.py

[BugFix] Support runtime-dependent vector negative indices (#2654)

2026-07-16 18:30:46 +08:00

test_tilelang_transform_legalize_vectorized_loop.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_transform_let_inline.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_lexical_alloc_scope.py

[TIR][Codegen] Preserve decoupled cast buffer scope (#2545)

2026-07-08 14:36:12 +08:00

test_tilelang_transform_loop_unswitching.py

[BugFix] Preserve loop steps during unswitching (#2741)

2026-07-23 14:41:19 +08:00

test_tilelang_transform_lower_device_kernel_launch.py

[BugFix] Use callee global symbols for cross-target calls (#2740)

2026-07-23 14:25:27 +08:00

test_tilelang_transform_lower_hopper_intrin.py

[CUDA] Reduce template include overhead (#2474)

2026-07-01 16:53:07 +08:00

test_tilelang_transform_lower_ldgstg.py

[Backend][Transform] Move backend-specific transforms into separate namespaces (#2297)

2026-06-02 11:25:10 +08:00

test_tilelang_transform_lower_shared_barrier.py

[Transform] Materialize kernel launch per backend (#2387)

2026-06-12 17:14:02 +08:00

test_tilelang_transform_lower_shared_tmem.py

[CUDA] Pack logical TMEM buffers into shared tcgen05.alloc arenas (#2831)

2026-08-03 13:53:12 +08:00

test_tilelang_transform_lower_tile_op.py

[Transform] Replace CPU fallback thread placeholder with a constant-zero logical thread index (#2718)

2026-07-21 18:23:19 +08:00

test_tilelang_transform_make_packed_api.py

[TIR][Runtime] Enforce host-evaluable assumptions at runtime (#2655)

2026-07-14 12:24:26 +08:00

test_tilelang_transform_pipeline_barrier_ownership.py

[Example] Migrate eligible examples to eager style (#2010)

2026-05-21 20:27:06 +08:00

test_tilelang_transform_pipeline_planning.py

[BugFix][Transform] Never classify side-effecting binds as replayable (atomics re-executed at every use site since v0.1.11) (#2651)

2026-07-22 17:43:01 +08:00

test_tilelang_transform_plan_update_buffer_allocation_location.py

[Backend][Transform] Move backend-specific transforms into separate namespaces (#2297)

2026-06-02 11:25:10 +08:00

test_tilelang_transform_preserve_loop_step.py

[BugFix] Correctly preserve loop step when unrolling loops (#2835)

2026-08-02 02:51:33 +08:00

test_tilelang_transform_producer_consumer_ws_persistent.py

[BugFix][WS] Fix pipeline replacement under persistent T.serial (#2674)

2026-07-20 18:53:13 +08:00

test_tilelang_transform_producer_consumer_ws.py

[BugFix] Skip descriptor TMA for device-bound copy bases (#2803)

2026-07-29 20:35:07 +08:00

test_tilelang_transform_simplify.py

[Transform] Place auto WS producers in first warp group (#2315)

2026-06-04 14:47:52 +08:00

test_tilelang_transform_smem_swizzle_alignment.py

[CUDA] Align swizzled TMA shared buffers (#2391)

2026-06-15 01:42:06 +08:00

test_tilelang_transform_split_host_device.py

[TIR][Runtime] Enforce host-evaluable assumptions at runtime (#2655)

2026-07-14 12:24:26 +08:00

test_tilelang_transform_thread_sync.py

[BugFix] Fix two-instance modeling in ThreadSync cross-thread race checks (#2805)

2026-07-30 19:15:08 +08:00

test_tilelang_transform_tmem_arena_packing.py

[CUDA] Pack logical TMEM buffers into shared tcgen05.alloc arenas (#2831)

2026-08-03 13:53:12 +08:00

test_tilelang_transform_tmem_physical_shape.py

[CUDA] Pack logical TMEM buffers into shared tcgen05.alloc arenas (#2831)

2026-08-03 13:53:12 +08:00

test_tilelang_transform_unroll_loop.py

[BugFix][Transform] Deduplicate DeclBuffer names after loop unrolling (#2290)

2026-05-29 01:03:43 +08:00

test_tilelang_transform_verify_parallel_loop.py

[Enhancement] Disable data race check by default, opt-in via env var (#2851)

2026-08-03 16:55:27 +08:00