Commit Graph
8 Commits
Author SHA1 Message Date
qutaoandClaude Opus 4.8 d3de762ce2 Merge origin/main into nvf4-block-scale-sm120
Resolve conflicts in merge_shared_memory_allocations.cc and codegen_cuda.cc:
upstream's new shared common/storage_size.h GetBufferStorageSizeBytes helper
covers the packed-FP4 exact-bits sizing this branch introduced (and extends
it to 4-bit integer types), so the sizing conflicts take the upstream side
and the branch-local sizing helpers are dropped. The NVFP4
byte-offset -> logical-index conversion in the non-alias rewrite stays, as
upstream has no equivalent. codegen_cuda.cc's 4-bit shared-allocation
handling was equivalently refactored upstream (is_byte_packed_4bit) and
already includes the scalar float4_e2m1fn case.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-21 18:56:30 +08:00
qutaoandClaude Opus 4.8 c48e37333c Group SM120 NVFP4 maint files and use native target API
Address maintainer review follow-ups:
- Move the four loose SM120 NVFP4 files under maint/gemm/ into a dedicated
  maint/gemm/gemm_sm120/ folder to distinguish them from other gemm types,
  updating the repo-root path resolution, the benchmark usage string, the
  cutlass_nvf4_ref.cu source path, and the quantizer loader in the scale-layout
  test.
- Guard the SM120-hardware test points with
  tilelang.testing.requires_cuda_compute_version_eq(12, 0): replace the manual
  capability skip in the example CLI test and tighten the block-scale kernel
  tests from _ge(12, 0) to _eq(12, 0).
- Reuse the native tilelang.cuda.target.target_is_sm120 helper in
  _is_explicit_non_sm120_cuda instead of hand-parsing the arch string, keeping
  the explicit-arch guard so targets without an arch attr never trip the C++
  ICHECK on hosts that have no SM120 GPU.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-21 16:56:18 +08:00
morluto 335afcf8a3 [BugFix] Decode FP8 E4M3 special encodings correctly (#2710) 2026-07-20 14:06:46 +08:00
qutaoandClaude Fable 5 87d99c2601 Keep tilelang.quantize to device helpers and format contract
tilelang/quantize's identity is device-side conversion helpers plus
host-side data-prep utilities (quantization.py's _tir_* converters, the
lop3/mxfp intrin groups); a complete quantizer operator does not belong
in the library. Move the TileLang BF16->NVFP4 kernel factory and its
dispatcher to maint/gemm/tilelang_nvfp4_quantizer.py, next to the maint
benchmark that consumes it.

nvfp4.py now carries exactly the format contract: the _tl_* device
helpers (FP4/UE4M3 encode/decode, scale-source coordinates) any user
kernel can call, the blockscaled_chunk_kmajor packers/swizzles, and the
torch reference quantizer — 524 lines (1334 at series start). The
package re-export list shrinks to the four user-facing names; the alias
wrappers are gone.

Validated: quantize + example CLI suites (35 passed), maint benchmark
and example --verify pass end-to-end.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-10 15:35:19 +08:00
qutaoandClaude Fable 5 f681a83779 Slim tilelang/quantize/nvfp4.py
Two structural reductions, no behavior change:

- Merge the three TMA-staged quantize kernel variants (16/32/64x256)
  into one _tilelang_nvfp4_blockscaled_quantize_kernel_tiled factory:
  their inner loops were line-identical, differing only in rows_per_cta,
  stage count and the store path (TMA store vs direct global stores),
  all of which are trace-time parameters now. Outputs verified
  bitwise-identical to the previous per-variant kernels for every
  dispatch configuration (quant bytes and scale source).
- Move the 14 SM120 OMMA scale-selector contract oracles into the
  contract test file that is their only consumer; the quantize module
  stays focused on quantization and layout packing.

1334 -> 978 lines. Quantize suite: 32 passed.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-10 15:21:00 +08:00
qutaoandClaude Fable 5 790a3f0ed1 Support M or N tail tiles in the SM120 NVFP4 example
Production shapes rarely keep M (batch x seq) a multiple of 128. Lift
the divisibility requirements to the validated envelope:

- scale packers zero-pad rows to full 128-row tiles (the same ceil
  convention CUTLASS/cuBLAS/CuTeDSL use for the blocked SF tensor), so
  the packed source always has ceil(rows/128)*128 rows;
- the example accepts an arbitrary M or an N tail: TMA loads zero-fill
  out-of-bounds rows and the C store is predicated. N keeps the
  16-byte-aligned-rows rule (N % 8 == 0), the same contiguous-dim
  alignment CuTeDSL validates;
- simultaneous M and N tails are rejected with a clear error: the
  fragment-to-global copy lowering emits the column guard bound from
  the wrong dimension in that case (upstream bug, tracked separately).

Tests: tail-shape runtime correctness (257x384, 130x128, 128x136 with
exact binary-scale references), rejection paths, and packer padding
round-trip.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-10 15:07:03 +08:00
qutaoandClaude Fable 5 66c8a30c2a Pin scale layout byte-compat with CuTeDSL blocked SF layout
blockscaled_chunk_kmajor packed words are byte-identical to the
CUTLASS/CuTeDSL canonical blocked SF layout (tile_atom_to_shape_SF,
sf_vec_size=16, atom ((32,4),(16,4)):((16,4),(0,1)) tiled with order
(2,1,3)); the two views bridge zero-copy via torch view casts. Document
that on the packer and lock it with a cross-layout contract test.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-10 14:02:15 +08:00
qutao 4de007ee84 Add SM120 NVFP4 blockscaled GEMM support 2026-07-10 14:02:15 +08:00