 Zhiyao JiangandXinyu Jiang
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8d22a2c345
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docs(AMD): Add an AMD ROCm page and fix the AMD image and hardware notes (#3209)
Co-authored-by: Xinyu Jiang <xinyuj2@andrew.cmu.edu>
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2026-09-17 18:13:19 -07:00 |
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Zhiyao Jiang
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a9844951d8
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fix(docker): bump torch_memory_saver to pick up the free-while-paused fix (#3192)
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2026-09-14 14:55:44 -07:00 |
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Zhiyao JiangandXinyu Jiang
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f328651715
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ci: Skip the actor forward-only pass in the Megatron FSDP-align test (#3166)
Co-authored-by: Xinyu Jiang <xinyuj2@andrew.cmu.edu>
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2026-09-09 22:56:42 -07:00 |
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Zhiyao Jiang
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031fe3d727
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ci: pin the DSv4 bshd/thd parity test to the miles impl (#3162)
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2026-09-09 15:59:02 -07:00 |
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7bf05390d7
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[feat] Enable THD packed-sequence training for DeepSeek-V4-Flash, with context parallelism (#2038)
Co-authored-by: Xinyu Jiang <xinyuj2@andrew.cmu.edu>
Co-authored-by: guapisolo <guapisolo@gmail.com>
Co-authored-by: Yueming Yuan <yym022502@gmail.com>
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2026-09-08 22:04:54 -07:00 |
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Zhiyao Jiang
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02098f1e59
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[AMD] Point the ROCm image at the v0.5.16 wheels release with TE 2.17.0 (#2660)
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2026-08-19 19:52:21 -07:00 |
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943b8acd52
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[AMD] Enable amd pr ci (#2347)
Co-authored-by: Xinyu Jiang <xinyuj2@andrew.cmu.edu>
Co-authored-by: Yuankai Chen <206619631+yuankaichen-amd@users.noreply.github.com>
Co-authored-by: Xinyu Kang <93342727+Xinyu-Kang@users.noreply.github.com>
Co-authored-by: Shekhar <38083203+indianspeedster@users.noreply.github.com>
Co-authored-by: Sree Rohith Pulipaka <119916571+sreerohi@users.noreply.github.com>
Co-authored-by: lizamd <161388580+lizamd@users.noreply.github.com>
Co-authored-by: Jiajun Li <guapisolo@gmail.com>
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2026-08-13 20:14:11 -07:00 |
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Zhiyao Jiang
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3507ce1543
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[AMD] retune AMD 4-node dsv4 config (#2139)
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2026-08-04 11:04:58 -07:00 |
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5c0c52f386
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[fp8] Gate the ue8m0 weight quantizer on the backend scale format (#2034)
Co-authored-by: Xinyu Jiang <xinyuj2@andrew.cmu.edu>
Co-authored-by: yueming-yuan <yym022502@gmail.com>
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2026-08-04 11:04:47 -07:00 |
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Zhiyao JiangandXinyu Jiang
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84ee8f3846
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[tiny] Make NVTE_FP8_BLOCK_SCALING_FP32_SCALES overridable via env (#1685)
Co-authored-by: Xinyu Jiang <xinyuj2@andrew.cmu.edu>
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2026-07-17 15:28:17 -07:00 |
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Zhiyao JiangandXinyu Jiang
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a60c23ce89
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[AMD] Add AMD MI350X/MI355X (gfx950) blockwise FP8 support for run_qwen3_30b_a3b (#1465)
Co-authored-by: Xinyu Jiang <xinyuj2@andrew.cmu.edu>
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2026-07-15 16:52:14 -07:00 |
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Zhiyao JiangandXinyu Jiang
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23335971f9
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[AMD] Fix HF to torch_dist conversion segfault during checkpoint save (#1604)
Co-authored-by: Xinyu Jiang <xinyuj2@andrew.cmu.edu>
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2026-07-09 17:40:07 -07:00 |
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Zhiyao JiangandXinyu Jiang
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83778ffd84
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[AMD] Enable R3 CI and add the rocm700-mi35x image variant (#1556)
Co-authored-by: Xinyu Jiang <xinyuj2@andrew.cmu.edu>
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2026-07-09 17:39:24 -07:00 |
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Zhiyao JiangandXinyu Jiang
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c5401d646a
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[AMD] Merge MI300/MI350-5 Dockerfiles (#1294)
Co-authored-by: Xinyu Jiang <xinyuj2@andrew.cmu.edu>
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2026-06-12 14:44:01 -07:00 |
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5dd0044e56
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Integrate Terminal Bench into Miles (#447)
Co-authored-by: Xinyu Jiang <xinyuj2@andrew.cmu.edu>
Co-authored-by: Jiajun Li <guapisolo@gmail.com>
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2026-01-16 23:29:39 -08:00 |
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