Lei Wang e3e71f0c87 [CUDA][IR] Preserve dynamic shared memory aliases (#2240) ...

* Preserve shared memory aliases after dynamic merge

* Enhance SharedMemoryRewriter to support alias preservation and buffer remapping during shared memory allocation merging

* lint fix

2026-05-21 18:12:58 +08:00

..

test_nullable_buffer_params.py

[BugFix] ArgBinder: relax shared-shape binding for unused nullable buffers (#1870)

2026-02-24 11:43:55 +08:00

test_readonly_param_const_codegen.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_transform_cluster_planning.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_config_index_bitwidth.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_transform_decouple_type_cast.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_disable_memory_reuse.py

[CUDA][IR] Preserve dynamic shared memory aliases (#2240)

2026-05-21 18:12:58 +08:00

test_tilelang_transform_flatten_buffer.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_fuse_mbarrier_arrive_expect_tx.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_hoist_broadcast_values.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_if_stmt_binding.py

[Transform] Preserve bind scope when splitting if statements (#2232)

2026-05-20 17:45:00 +08:00

test_tilelang_transform_inject_fence_proxy.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_inject_set_max_nreg.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_Inject_software_pipeline.py

[Pipeline] Support scalar bind-free pipeline annotations (#2237)

2026-05-21 15:20:18 +08:00

test_tilelang_transform_inject_tcgen05_fence.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_layout_inference.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_legalize_negative_index.py

[Enhancement]Support mixed-sign ramp indices in LegalizeNegativeIndex (#2225)

2026-05-19 18:03:43 +08:00

test_tilelang_transform_legalize_safe_memory_access.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_legalize_vectorized_loop.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_transform_let_inline.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_lexical_alloc_scope.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_loop_unswitching.py

[BugFix] LoopUnswitching: gate non-trivial else behind PassConfig (#1816)

2026-02-09 11:20:20 +08:00

test_tilelang_transform_lower_hopper_intrin.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_lower_ldgstg.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_lower_ptx_async_copy.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_lower_shared_barrier.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_lower_shared_tmem.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_lower_tile_op.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_make_packed_api.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_pipeline_barrier_ownership.py

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

test_tilelang_transform_pipeline_planning.py

[Pipeline] Support scalar bind-free pipeline annotations (#2237)

2026-05-21 15:20:18 +08:00

test_tilelang_transform_plan_update_buffer_allocation_location.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_producer_consumer_ws.py

[Transform] Preserve WS prelude liveness ordering (#2233)

2026-05-21 00:41:21 +08:00

test_tilelang_transform_simplify.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_split_host_device.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_thread_sync.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00