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T.__ldg failed to compile for float16 and bfloat16 buffers because CUDA provides __ldg overloads for __half and __nv_bfloat16, while TileLang uses CUTLASS half_t and bfloat16_t for these scalar types. Add forwarding overloads in common.h that reinterpret the bit-compatible pointers as the native CUDA types and wrap the loaded values back in the CUTLASS types. The native 16-bit __ldg is available on SM60+, so no architecture-specific fallback is needed. Update the stale 32-bit-only API wording and add exact round-trip coverage for both dtypes.
57 lines
1.6 KiB
Python
57 lines
1.6 KiB
Python
import pytest
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import torch
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import tilelang
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import tilelang.language as T
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import tilelang.testing
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@tilelang.testing.requires_cuda
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def test_language_ldg_codegen():
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N = 128
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@T.prim_func
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def main(
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x: T.Tensor((N,), T.float32),
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y: T.Tensor((N,), T.float32),
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):
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with T.Kernel(N, threads=32) as pid:
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# Explicitly request read-only cache load for x[pid]
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y[pid] = T.__ldg(x[pid]) + 1.0
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# Compile for CUDA and retrieve generated CUDA source
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kernel = tilelang.compile(main, out_idx=[1], target="cuda")
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src = kernel.get_kernel_source()
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print(src)
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# Assert that codegen uses __ldg on CUDA backend
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# We look for the intrinsic call with address-of argument
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assert "__ldg(" in src, "Expected __ldg call in generated CUDA source"
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assert "__ldg(&" in src or "__ldg(&(" in src, "Expected address-of form in __ldg call"
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def run_ldg_roundtrip(dtype, N=128):
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@T.prim_func
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def main(
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x: T.Tensor((N,), dtype),
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y: T.Tensor((N,), dtype),
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):
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with T.Kernel(N, threads=32) as pid:
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y[pid] = T.__ldg(x[pid])
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kernel = tilelang.compile(main, out_idx=[1], target="cuda")
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# Match the address-of form emitted by CUDA codegen.
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assert "__ldg(&(" in kernel.get_kernel_source()
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x = torch.randn(N, device="cuda").to(dtype.as_torch())
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assert torch.equal(kernel(x), x)
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@tilelang.testing.requires_cuda
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@pytest.mark.parametrize("dtype", [T.float16, T.bfloat16])
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def test_language_ldg_roundtrip(dtype):
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run_ldg_roundtrip(dtype)
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if __name__ == "__main__":
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tilelang.testing.main()
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