mirror of
https://github.com/tile-ai/tilelang.git
synced 2026-10-24 07:04:00 +08:00
Lei Wang
7c98e990a7
* [Debug][TIR] Unify pass tracing on PassInstrument * [Debug] Fix context manager generator annotations * [Debug] Scope pass instrumentation per compile * [JIT] Require lowered modules in source adapters * [Debug] Manage pass timing through compile sessions * [JIT] Clarify compile session orchestration * [JIT] Clarify compile metadata naming * [Debug] Simplify instrumentation session boundaries * [Debug] Clarify instrumentation execution boundaries * [Debug] Organize pass instrumentation infrastructure * [Debug] Trim redundant instrumentation tests
18 lines
446 B
Python
18 lines
446 B
Python
import pytest
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from tilelang import tvm
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from tilelang.jit.adapter.wrapper import TLCPUSourceWrapper
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def test_adapter_source_wrapper_requires_lowered_modules():
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with pytest.raises(ValueError, match="missing: device_mod, host_mod"):
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TLCPUSourceWrapper(
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scheduled_ir_module=tvm.IRModule(),
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source="",
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target=tvm.target.Target("c"),
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)
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if __name__ == "__main__":
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pytest.main([__file__])
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