mirror of
https://github.com/tile-ai/tilelang.git
synced 2026-10-20 06:30:07 +08:00
Lei Wang
a91bc2a9fb
* Add example for warp specialization with flash attention * Introduced a new example script `example_warp_specialize_flashmla.py` demonstrating flash attention using warp specialization in TileLang. * Implemented the `flashattn` function with shared memory allocation and memory barrier synchronization for improved performance. * Added a reference program for validation against PyTorch's implementation, including profiling for latency and performance metrics. * Removed the outdated `example_warp_specialize_mla.py` to streamline examples and focus on the new implementation. * Add memory barrier functions to builtin.py * Introduced `barrier_wait` and `barrier_arrive` functions for memory barrier synchronization. * Enhanced documentation with detailed docstrings for both functions, clarifying their usage and parameters. * The `barrier_wait` function serves as a wrapper for `mbarrier_wait_parity`, supporting parity values 0 and 1. * Improved code organization and readability by adding blank lines for better separation of logical sections. * Enhance code readability by adding blank lines in example_warp_specialize_flashmla.py and builtin.py * Added blank lines to improve code organization and separation of logical sections in `example_warp_specialize_flashmla.py`. * Included blank lines in `builtin.py` around the `wait_wgmma` and `barrier_wait` functions for better readability. * [Refactor] Update barrier functions and add new example for GEMM with warp specialization * Refactored memory barrier functions in `example_warp_specialize_flashmla.py` to use the new `barrier_wait` and `barrier_arrive` methods for improved clarity and consistency. * Introduced a new example script `example_warp_specialize_gemm_copy_gemm_0_1.py` demonstrating matrix multiplication with warp specialization and shared memory allocation. * Enhanced the `layout.cc` and `elem.cc` files to improve structural equality checks and error handling in copy operations. * Updated `warpgroup.py` to refine thread ID calculations for better performance in warp specialization scenarios. * Added new shuffle operations in `builtin.py` for enhanced functionality in parallel computations. * lint fix * Update loop variable checks in SIMT loop and buffer region validation * Modified checks in `elem.cc` to ensure loop variable sizes are less than or equal to source and destination range sizes for better error handling. * Adjusted assertions in `copy.py` to reflect the updated logic, allowing for more flexible region extent comparisons and improved error messaging. * lint fix * test fix
642 lines
23 KiB
Python
642 lines
23 KiB
Python
import torch
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import torch.backends
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import tilelang.testing
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from tilelang import tvm as tvm
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from tvm import DataType, tir
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import tilelang.language as T
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tilelang.testing.set_random_seed(0)
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def _tir_u8_to_f4_to_f16(nbit: int, val: tir.PrimExpr, pos: tir.PrimExpr, dtype: str):
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assert nbit == 4
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assert dtype == "float16"
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assert val.dtype == "uint8"
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# e_f4 == 0 -> e_f16 = 0
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# e_f4 != 0 -> e_f16 = e_f4 + 8 = e_f4 | (1000)_2
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# s1e2n1
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mask = tir.const((1 << nbit) - 1, "uint16")
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f4 = (val >> (pos.astype("uint16") * tir.const(nbit, "uint16"))) & mask
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s = f4 >> tir.const(3, "uint16")
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e_f4 = f4 & tir.const(7, "uint16")
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e_f16 = e_f4 | tir.const(8, "uint16")
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val_f16 = tir.reinterpret(
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"float16",
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((e_f16 | (s << tir.const(5, "uint16"))) << tir.const(10, "uint16")).astype("uint16"))
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# return tir.Select(e_f4 == tir.const(0, "uint32"), tir.const(0, "float16"), val_f16)
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return val_f16
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def torch_convert(tensor):
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def print_bit(name, val):
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val_cpu = val.cpu().item()
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binary_repr = f'{val_cpu:032b}'
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print(name, binary_repr)
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def _convert(val, pos):
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assert val.dtype == torch.uint8
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val = val.view(torch.int8)
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mask = (1 << 4) - 1
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f4 = ((val >> (pos * 4)) & mask).to(torch.int16)
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s = f4 >> 3
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e_f4 = f4 & 7
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e_f16 = e_f4 | 8
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val_f16 = ((e_f16 | (s << 5)) << 10) & 0xFFFF
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lower_16_bits = (val_f16 & 0xFFFF).to(torch.uint16)
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return lower_16_bits.view(torch.float16)
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N = tensor.shape[0]
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K = tensor.shape[1]
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new_tensor = torch.empty(N, K * 2, dtype=torch.float16, device=tensor.device)
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for i in range(new_tensor.shape[0]):
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for j in range(new_tensor.shape[1]):
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new_tensor[i][j] = _convert(tensor[i][j // 2], j % 2)
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return new_tensor
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def _convert_test(N, K, block_N, block_K, in_dtype, num_bits=4, threads=128):
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num_elems_per_byte = 8 // num_bits
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storage_dtype = "uint8"
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B_shape = (N, K // num_elems_per_byte)
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B_shared_shape = (block_N, block_K // num_elems_per_byte)
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B_dequantize_shared_shape = (block_N, block_K)
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@T.prim_func
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def main(
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B: T.Tensor(B_shape, storage_dtype),
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C: T.Tensor((N, K), in_dtype),
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):
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with T.Kernel(T.ceildiv(N, block_N), threads=threads) as (bx):
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B_shared = T.alloc_shared(B_shared_shape, storage_dtype)
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B_local = T.alloc_fragment(B_shared_shape, storage_dtype)
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B_dequantize_local = T.alloc_fragment(B_dequantize_shared_shape, in_dtype)
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for k in T.Pipelined(T.ceildiv(K, block_K), num_stages=1):
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T.copy(B[bx * block_N, k * block_K // num_elems_per_byte], B_shared)
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T.copy(B_shared, B_local)
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for i, j in T.Parallel(block_N, block_K):
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B_dequantize_local[i, j] = _tir_u8_to_f4_to_f16(
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num_bits,
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B_local[i, j // num_elems_per_byte],
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j % num_elems_per_byte,
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dtype=in_dtype,
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)
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T.copy(B_dequantize_local, C[bx * block_N, k * block_K])
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return main
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def test_fp4_fp16_convert_close():
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N, K = 256, 256
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block_N, block_K = 64, 64
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program = _convert_test(
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N,
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K,
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block_N,
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block_K,
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"float16",
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)
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kernel = tilelang.compile(program, out_idx=[1])
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B = torch.randint(0, 16, (N, K // 2), dtype=torch.uint8, device="cuda").to(torch.uint8)
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tl_out = kernel(B)
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ref_out = torch_convert(B)
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assert torch.allclose(tl_out, ref_out, rtol=0.01, atol=0.01), (tl_out, ref_out)
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print("Pass")
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def matmul_fp16xfp4(M,
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N,
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K,
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in_dtype,
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out_dtype,
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accum_dtype,
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block_M=64,
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block_N=64,
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block_K=64,
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num_stages=1,
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threads=128):
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num_bits = 4
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def kernel_func(block_M, block_N, block_K, num_stages, threads):
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num_elems_per_byte = 8 // num_bits
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storage_dtype = "uint8"
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A_shape = (M, K)
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B_shape = (N, K // num_elems_per_byte)
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A_shared_shape = (block_M, block_K)
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B_shared_shape = (block_N, block_K // num_elems_per_byte)
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B_dequantize_shared_shape = (block_N, block_K)
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assert K % (block_K) == 0
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@T.prim_func
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def main(
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A: T.Tensor(A_shape, in_dtype),
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B: T.Tensor(B_shape, storage_dtype),
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Ct: T.Tensor((N, M), out_dtype),
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):
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with T.Kernel(
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T.ceildiv(N, block_N), T.ceildiv(M, block_M), threads=threads) as (bx, by):
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A_shared = T.alloc_shared(A_shared_shape, in_dtype)
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B_shared = T.alloc_shared(B_shared_shape, storage_dtype)
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B_local = T.alloc_fragment(B_shared_shape, storage_dtype)
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B_dequantize_local = T.alloc_fragment(B_dequantize_shared_shape, in_dtype)
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B_dequantize_prev_local = T.alloc_fragment(B_dequantize_shared_shape, in_dtype)
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Ct_local = T.alloc_fragment((block_N, block_M), accum_dtype)
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Ct_shared = T.alloc_shared((block_N, block_M), out_dtype)
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T.annotate_layout({
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B_shared: tilelang.layout.make_swizzled_layout(B_shared),
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Ct_shared: tilelang.layout.make_swizzled_layout(Ct_shared),
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})
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T.clear(Ct_local)
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for k in T.Pipelined(K // block_K, num_stages=num_stages):
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T.copy(A[by * block_M, k * block_K], A_shared)
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T.copy(B[bx * block_N, k * block_K // num_elems_per_byte], B_shared)
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T.copy(B_shared, B_local)
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for i, j in T.Parallel(block_N, block_K):
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B_dequantize_local[i, j] = _tir_u8_to_f4_to_f16(
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num_bits,
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B_local[i, j // num_elems_per_byte],
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j % num_elems_per_byte,
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dtype=in_dtype,
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)
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T.copy(B_dequantize_local, B_dequantize_prev_local)
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T.gemm(B_dequantize_prev_local, A_shared, Ct_local, transpose_B=True)
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T.copy(Ct_local, Ct_shared)
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T.copy(Ct_shared, Ct[bx * block_N:(bx + 1) * block_N,
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by * block_M:(by + 1) * block_M])
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return main
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return kernel_func(
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block_M=block_M, block_N=block_N, block_K=block_K, num_stages=num_stages, threads=threads)
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def ref_program(A, qB):
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dtypeC = "float16"
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B = torch_convert(qB)
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C = torch.matmul(A.to(torch.float), B.T.to(torch.float))
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C = C.to(torch.__getattribute__(dtypeC))
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return C.transpose(0, 1)
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def assert_simple_impl_float16xfp4_gemm(M,
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N,
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K,
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in_dtype,
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out_dtype,
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accum_dtype,
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block_M=64,
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block_N=64,
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block_K=64,
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num_stages=1,
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threads=128):
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func = matmul_fp16xfp4(M, N, K, in_dtype, out_dtype, accum_dtype, block_M, block_N, block_K,
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num_stages, threads)
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torch_func = tilelang.compile(func, out_idx=[2])
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profiler = torch_func.get_profiler()
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profiler.assert_allclose(ref_program)
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def test_simple_impl_float16xfp4_gemm():
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assert_simple_impl_float16xfp4_gemm(256, 256, 256, "float16", "float16", "float32", 64, 64, 64,
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1, 128)
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def matmul(
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M,
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N,
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K,
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block_M,
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block_N,
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block_K,
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in_dtype,
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out_dtype,
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accum_dtype,
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num_stages,
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threads,
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num_bits=4,
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):
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from bitblas.quantization import _tir_packed_to_unsigned_convert
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num_elems_per_byte = 8 // num_bits
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storage_dtype = "int8"
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storage_nbit = int("".join(c for c in storage_dtype if c.isdigit()))
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storage_type = str("".join(c for c in storage_dtype if not c.isdigit()))
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A_shape = (M, K)
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B_shape = (N, K // num_elems_per_byte)
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A_shared_shape = (block_M, block_K)
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B_shared_shape = (block_N, block_K // num_elems_per_byte)
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B_dequantize_shared_shape = (block_N, block_K)
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MAX_TRANSACTION_SIZE_IN_BITS = 128
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local_size = MAX_TRANSACTION_SIZE_IN_BITS // DataType(in_dtype).bits
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local_size_compressed = local_size // num_elems_per_byte
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import tilelang.language as T
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@T.prim_func
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def main(
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A: T.Tensor(A_shape, in_dtype),
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B: T.Tensor(B_shape, storage_dtype),
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C: T.Tensor((M, N), out_dtype),
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):
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with T.Kernel(T.ceildiv(N, block_N), T.ceildiv(M, block_M), threads=threads) as (bx, by):
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A_shared = T.alloc_shared(A_shared_shape, in_dtype)
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B_shared = T.alloc_shared(B_shared_shape, storage_dtype)
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B_local = T.alloc_local([local_size_compressed], storage_dtype)
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B_dequantize_local = T.alloc_local([local_size], in_dtype)
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B_dequantize_shared = T.alloc_shared(B_dequantize_shared_shape, in_dtype)
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C_local = T.alloc_fragment((block_M, block_N), accum_dtype)
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tx = T.get_thread_binding()
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T.clear(C_local)
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for k in T.Pipelined(T.ceildiv(K, block_K), num_stages=num_stages):
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T.copy(A[by * block_M, k * block_K], A_shared)
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T.copy(B[bx * block_N, k * block_K // num_elems_per_byte], B_shared)
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for i in T.serial(block_N * block_K // num_elems_per_byte //
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(threads * local_size_compressed)):
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for v in T.vectorized(0, local_size_compressed):
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index = i * threads * local_size_compressed + tx * local_size_compressed + v
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vi = index // (block_K // num_elems_per_byte)
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vj = index % (block_K // num_elems_per_byte)
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B_local[v] = B_shared[vi, vj]
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for v in T.serial(0, local_size):
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B_dequantize_local[v] = _tir_packed_to_unsigned_convert(
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storage_type, storage_nbit)(
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num_bits,
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B_local[v // num_elems_per_byte],
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v % num_elems_per_byte,
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dtype=in_dtype,
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)
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for v in T.vectorized(0, local_size):
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index = i * threads * local_size + tx * local_size + v
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vi = index // block_K
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vj = index % block_K
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B_dequantize_shared[vi, vj] = B_dequantize_local[v]
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T.gemm(A_shared, B_dequantize_shared, C_local, transpose_B=True)
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T.copy(C_local, C[by * block_M, bx * block_N])
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return main
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def run_gemm(
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M,
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N,
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K,
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in_dtype,
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out_dtype,
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dtypeAccum,
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block_M,
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block_N,
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block_K,
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num_stages=3,
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num_threads=128,
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):
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program = matmul(
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M,
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N,
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K,
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block_M,
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block_N,
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block_K,
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in_dtype,
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out_dtype,
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dtypeAccum,
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num_stages,
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num_threads,
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)
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kernel = tilelang.compile(program, out_idx=[2])
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profiler = kernel.get_profiler()
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out = profiler.run_once()
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assert out is not None
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def ref_program(A, qB):
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import torch
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B = (
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torch.zeros(qB.shape[0], qB.shape[1] * 8 // 4,
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dtype=torch.half).to(torch.half).to(A.device))
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for i in range(B.shape[0]):
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for j in range(B.shape[1]):
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B[i][j] = ((qB[i][j // 2] >> (4 * (j % 2))) & 0xF).to(torch.half)
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C = torch.matmul(A.to(torch.float), B.T.to(torch.float))
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C = C.to(torch.__getattribute__(out_dtype))
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return C
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profiler.assert_allclose(ref_program)
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@tvm.testing.requires_package("bitblas")
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@tilelang.testing.requires_llvm
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def tl_matmul_with_ladder_weight_only_transform_block_reduce_int4(
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M,
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N,
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K,
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in_dtype,
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out_dtype,
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accum_dtype,
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transform_b,
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):
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from tilelang.intrinsics.mma_layout import make_mma_swizzle_layout as make_swizzle_layout
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from tilelang.intrinsics.mma_macro_generator import (
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TensorCoreIntrinEmitterWithLadderTransform,)
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from bitblas.gpu.intrin.lop3 import decode_i4_to_f16
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assert in_dtype in [
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"float16",
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"int8",
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], "Currently only float16 and int8 are supported"
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assert out_dtype in [
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"float16",
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"float32",
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"int32",
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], "Currently only float16, float32 and int32 are supported"
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num_bits = 4
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num_elems_per_byte = 8 // num_bits
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storage_dtype = "int8"
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micro_size_x = micro_size_y = micro_size_k = 16
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if out_dtype == "int32":
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micro_size_k = 32
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# This is a debug config
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block_row_warps = 2
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block_col_warps = 2
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warp_rows = 4
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warp_cols = 4
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warp_row_tiles = micro_size_x * warp_rows
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warp_col_tiles = micro_size_y * warp_cols
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shared_scope = "shared.dyn"
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# Pipeline Stage
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stage = 2
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reduce_k = 1
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block_M = block_row_warps * warp_row_tiles
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block_N = block_col_warps * warp_col_tiles
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block_K = 32 if in_dtype == "float16" else 64
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chunk = block_K // reduce_k
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is_smooth_a = False
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can_swizzle = block_K * DataType(in_dtype).bits == 512
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apply_pad_a = not (is_smooth_a or can_swizzle)
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pad_factor = 8
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A_shape = (M, K)
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B_shape = (N // micro_size_y, K // micro_size_k, micro_size_y,
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micro_size_k // num_elems_per_byte)
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A_shared_shape = (block_M, (block_K + pad_factor) if apply_pad_a else block_K)
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B_shared_shape = (
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block_N // micro_size_y,
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block_K // micro_size_k,
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micro_size_y,
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micro_size_k // num_elems_per_byte,
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)
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C_shared_shape = (
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block_M // micro_size_x,
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block_N // micro_size_y,
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micro_size_x,
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micro_size_y,
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)
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warp_size = 32
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threads = warp_size * (block_row_warps * block_col_warps)
|
|
local_size = (micro_size_x * micro_size_y) // warp_size
|
|
warp_rows = warp_row_tiles // micro_size_x
|
|
warp_cols = warp_col_tiles // micro_size_y
|
|
|
|
# MMA Wrapper to Auto Generate Code for MMA
|
|
mma_emitter = TensorCoreIntrinEmitterWithLadderTransform(
|
|
a_dtype=in_dtype,
|
|
b_dtype=in_dtype,
|
|
accum_dtype=accum_dtype,
|
|
a_transposed=False,
|
|
b_transposed=True,
|
|
block_row_warps=block_row_warps,
|
|
block_col_warps=block_col_warps,
|
|
warp_row_tiles=warp_row_tiles,
|
|
warp_col_tiles=warp_col_tiles,
|
|
chunk=chunk,
|
|
reduce_k=reduce_k,
|
|
transform_kind_b=transform_b,
|
|
num_elems_per_byte=num_elems_per_byte)
|
|
|
|
vec_load_qb = 16
|
|
if block_N * (block_K // reduce_k) // num_elems_per_byte // threads < vec_load_qb:
|
|
vec_load_qb = block_N * (block_K // reduce_k) // num_elems_per_byte // threads
|
|
|
|
@T.prim_func
|
|
def main(
|
|
A: T.Tensor(A_shape, in_dtype),
|
|
B: T.Tensor(B_shape, storage_dtype),
|
|
C: T.Tensor((M, N), out_dtype),
|
|
):
|
|
with T.Kernel(
|
|
T.ceildiv(N, block_N), T.ceildiv(M, block_M), threads=threads,
|
|
prelude=decode_i4_to_f16) as (bx, by):
|
|
|
|
A_shared = T.alloc_shared(A_shared_shape, in_dtype, scope=shared_scope)
|
|
B_shared = T.alloc_shared(B_shared_shape, storage_dtype, scope=shared_scope)
|
|
C_shared = T.alloc_shared(C_shared_shape, out_dtype, scope=shared_scope)
|
|
A_local = T.alloc_local((warp_rows * local_size), in_dtype)
|
|
B_local = T.alloc_local((warp_cols * local_size // num_elems_per_byte), storage_dtype)
|
|
B_dequantize_local = T.alloc_local((warp_cols * local_size), in_dtype)
|
|
C_local = T.alloc_local((warp_rows * warp_cols * local_size), accum_dtype)
|
|
reduced_accum_res = T.alloc_local(0, accum_dtype)
|
|
thread_binding = T.get_thread_binding(0)
|
|
rk = T.get_thread_binding(1)
|
|
|
|
T.annotate_layout({
|
|
A_shared: make_swizzle_layout(A_shared),
|
|
})
|
|
|
|
T.use_swizzle(panel_size=10)
|
|
|
|
T.clear(C_local)
|
|
|
|
for ko in T.Pipelined((K // block_K), num_stages=stage):
|
|
|
|
# Load A into shared memory
|
|
for i, k in T.Parallel(block_M, (block_K // reduce_k)):
|
|
vk = rk * (block_K // reduce_k) + k
|
|
A_shared[i, vk] = A[by * block_M + i, ko * block_K + vk]
|
|
|
|
# TODO(lei): Layout Inference Pass is not efficient to handle the four dims int8 load
|
|
for i in T.serial(block_N * (block_K // reduce_k) // num_elems_per_byte //
|
|
(threads * vec_load_qb)):
|
|
for v in T.vectorized(0, vec_load_qb):
|
|
t = thread_binding
|
|
idx = i * threads * vec_load_qb * reduce_k + rk * threads * vec_load_qb + t * vec_load_qb + v
|
|
vkk = idx % (micro_size_k // num_elems_per_byte)
|
|
vjj = (idx // (micro_size_k // num_elems_per_byte)) % micro_size_y
|
|
vk = (idx // (micro_size_k // num_elems_per_byte) // micro_size_y) % (
|
|
block_K // micro_size_k)
|
|
vj = (idx // (micro_size_k // num_elems_per_byte) // micro_size_y //
|
|
(block_K // micro_size_k)) % (
|
|
block_N // micro_size_y)
|
|
B_shared[vj, vk, vjj,
|
|
vkk] = B[bx * (block_N // micro_size_y) + vj,
|
|
ko * (block_K // micro_size_k) + vk, vjj, vkk]
|
|
|
|
for ki in T.serial(0, (block_K // (micro_size_k * reduce_k))):
|
|
|
|
# Load A into fragment
|
|
mma_emitter.ldmatrix_a(
|
|
A_local,
|
|
A_shared,
|
|
ki,
|
|
rk=rk,
|
|
)
|
|
|
|
# Load B into fragment
|
|
mma_emitter.ldmatrix_b(
|
|
B_local,
|
|
B_shared,
|
|
ki,
|
|
rk=rk,
|
|
)
|
|
|
|
for j in T.serial(warp_cols):
|
|
local_size_b = mma_emitter.local_size_b
|
|
T.call_extern('handle', 'decode_i4u_to_f16',
|
|
T.address_of(B_local[j * local_size_b // num_elems_per_byte]),
|
|
T.address_of(B_dequantize_local[j * local_size_b]), 8)
|
|
|
|
mma_emitter.mma(A_local, B_dequantize_local, C_local)
|
|
|
|
if reduce_k > 1:
|
|
for n in T.serial(warp_rows * warp_cols * local_size):
|
|
T.attr(
|
|
T.comm_reducer(lambda x, y: x + y, [T.float16(0)]),
|
|
"reduce_scope",
|
|
T.reinterpret(T.uint64(0), dtype="handle"),
|
|
)
|
|
T.evaluate(
|
|
T.tvm_thread_allreduce(
|
|
T.uint32(1),
|
|
C_local[n],
|
|
True,
|
|
reduced_accum_res[0],
|
|
rk,
|
|
dtype="handle",
|
|
))
|
|
if rk == 0:
|
|
C_local[n] = reduced_accum_res[0]
|
|
|
|
if rk == 0:
|
|
mma_emitter.stmatrix(
|
|
C_local,
|
|
C_shared,
|
|
)
|
|
|
|
for i, j in T.Parallel(block_M, (block_N // reduce_k)):
|
|
vj = rk * (block_N // reduce_k) + j
|
|
C[by * block_M + i,
|
|
bx * block_N + vj] = C_shared[i // micro_size_x, vj // micro_size_y,
|
|
i % micro_size_x, vj % micro_size_y]
|
|
|
|
return main
|
|
|
|
|
|
def assert_tl_matmul_with_ladder_weight_only_transform_block_reduce_int4_correctness(
|
|
M,
|
|
N,
|
|
K,
|
|
in_dtype,
|
|
out_dtype,
|
|
accum_dtype,
|
|
transform_b,
|
|
):
|
|
import bitblas
|
|
matmul = tl_matmul_with_ladder_weight_only_transform_block_reduce_int4(
|
|
M, N, K, in_dtype, out_dtype, accum_dtype, transform_b)
|
|
|
|
kernel = tilelang.compile(matmul, out_idx=[2])
|
|
profiler = kernel.get_profiler()
|
|
|
|
src_code = kernel.get_kernel_source()
|
|
|
|
# src_code is the generated cuda source
|
|
assert src_code is not None
|
|
num_bits = 4
|
|
num_elems_per_byte = 8 // num_bits
|
|
storage_dtype = "int8"
|
|
|
|
A = torch.rand(M, K, device="cuda", dtype=getattr(torch, in_dtype))
|
|
qB = torch.randint(
|
|
0, 127, (N, K // num_elems_per_byte), device="cuda", dtype=getattr(torch, storage_dtype))
|
|
C = torch.zeros(M, N, device="cuda", dtype=getattr(torch, accum_dtype))
|
|
|
|
ladder_permutate_config = bitblas.ops.LadderPermutateConfig(
|
|
M=N,
|
|
N=K,
|
|
transform_kind=transform_b,
|
|
transpose_matrix=True,
|
|
dequantize_bits=num_bits,
|
|
storage_dtype=storage_dtype,
|
|
)
|
|
|
|
ladder_permutate = bitblas.ops.LadderPermutate(ladder_permutate_config)
|
|
|
|
lop3_permutate_config = bitblas.ops.LOP3PermutateConfig(
|
|
M=N,
|
|
N=K,
|
|
datatype=in_dtype,
|
|
dequantize_bits=num_bits,
|
|
storage_dtype=storage_dtype,
|
|
)
|
|
lop3_permutate = bitblas.ops.LOP3Permutate(
|
|
config=lop3_permutate_config,
|
|
target=tvm.target.Target("llvm"),
|
|
)
|
|
QLB = ladder_permutate(qB.cpu()).cuda()
|
|
QLB = lop3_permutate(QLB.cpu()).cuda()
|
|
|
|
C = kernel(A, QLB)
|
|
|
|
latency = profiler.do_bench()
|
|
|
|
# Ensure that the latency is not None
|
|
assert latency is not None
|
|
|
|
B = (
|
|
torch.zeros(qB.shape[0], qB.shape[1] * 8 // 4,
|
|
dtype=torch.half).to(torch.half).to(A.device))
|
|
for i in range(B.shape[0]):
|
|
for j in range(B.shape[1]):
|
|
B[i][j] = ((qB[i][j // 2] >> (4 * (j % 2))) & 0xF).to(torch.half)
|
|
|
|
# Get Reference Result
|
|
ref_c = torch.matmul(A, B.T).to(getattr(torch, accum_dtype))
|
|
print("Ref C: ", ref_c)
|
|
print("C: ", C)
|
|
torch.testing.assert_close(C, ref_c, rtol=1e-2, atol=1e-2)
|
|
|
|
|
|
@tilelang.testing.requires_package("bitblas")
|
|
def test_run_dequantize_gemm():
|
|
run_gemm(256, 256, 256, "float16", "float16", "float16", 128, 128, 32, num_threads=128)
|
|
run_gemm(256, 256, 256, "int8", "int32", "int32", 128, 128, 32, num_threads=128)
|
|
|
|
|
|
@tilelang.testing.requires_package("bitblas")
|
|
@tilelang.testing.requires_llvm
|
|
def test_assert_tl_matmul_with_ladder_weight_only_transform_block_reduce_int4():
|
|
assert_tl_matmul_with_ladder_weight_only_transform_block_reduce_int4_correctness(
|
|
256, 1024, 512, "float16", "float16", "float16", 3)
|
|
|
|
|
|
if __name__ == "__main__":
|
|
tilelang.testing.main()
|