Kasper Nielsen d135bd1cd2 fix: TMA alignment to 1024 bytes on Blackwell (#2134) ...

* fix: TMA alignment to 1024 bytes on Blackwell

Previously 1024 byte alignemnt was guarded only by `IsHopper`.
This commit changes it to be guarded by `TargetHasBulkCopy` with the
same threshold as Hopper is using.

The kernel added in the test was failing on my RTX5090 GPU.

* Fix lint

2026-05-04 00:12:02 +08:00

..

test_tilelang_issue_96.py

[Bugfix] Open Rocm ci test and fix some bugs. (#1443)

2026-01-06 02:18:29 +08:00

test_tilelang_issue_814.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_issue_830.py

[Bugfix] Open Rocm ci test and fix some bugs. (#1443)

2026-01-06 02:18:29 +08:00

test_tilelang_issue_1001.py

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

test_tilelang_issue_1008.py

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

test_tilelang_issue_1026.py

[Feature] Reimplement Threadsync with ConstrVisitor (#1631)

2026-01-15 18:59:50 +08:00

test_tilelang_issue_1115.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_issue_1198.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_issue_1210.py

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

test_tilelang_issue_1237.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_issue_1257.py

[Refactor] Introduce T.access_of to combine T.address_of and access_ptr (#1827)

2026-02-11 22:51:59 +08:00

test_tilelang_issue_1263.py

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

test_tilelang_issue_1374.py

[Feat] Add strong checker to detect data racing in T.Parallel (#1615)

2026-01-06 17:31:24 +08:00

test_tilelang_issue_1549.py

[Refactor] Unify @jit and @lazy_jit into a single @jit decorator (#1632)

2026-01-09 15:41:39 +08:00

test_tilelang_issue_1601.py

[Refactor] Unify @jit and @lazy_jit into a single @jit decorator (#1632)

2026-01-09 15:41:39 +08:00

test_tilelang_issue_1604.py

[Feature] Reimplement Threadsync with ConstrVisitor (#1631)

2026-01-15 18:59:50 +08:00

test_tilelang_issue_1678.py

[Bugfix][Refactor] Always disable light storage reuse (#1691)

2026-01-19 18:06:35 +08:00

test_tilelang_issue_1690.py

[EagerJIT] Lazy Evaluation of Kernel Body in Eager JIT (#1690) (#1694)

2026-01-23 14:33:12 +08:00

test_tilelang_issue_1697.py

[BugFix] Stride check and fix for tensors with zero-stride argument (#1749)

2026-01-29 23:59:24 +08:00

test_tilelang_issue_1719.py

[Layout] Fix Layout Bugs in Parallel and Reduce (#1713)

2026-01-28 10:56:25 +08:00

test_tilelang_issue_1728.py

[BugFix] Remove unnecessary binding in loop variable analysis and add test for issue 1728 (#1735)

2026-01-27 14:43:28 +08:00

test_tilelang_issue_1734.py

[Feature] Support Pass LoopUnswitching (#1747)

2026-02-01 00:32:51 +08:00

test_tilelang_issue_1744.py

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

test_tilelang_issue_1810.py

[BugFix] Fix fp16 annotate_l2_hit_ratio host stub compilation (issue #1810) (#1818)

2026-02-09 13:26:17 +08:00

test_tilelang_issue_1846.py

[BugFix] Fix eager mode where there is no tensor args (#1851)

2026-02-16 00:34:10 +08:00

test_tilelang_issue_1993.py

[Bugfix] Raise error on zero grid dimension instead of silent clamp (#1994)

2026-03-30 16:14:35 +08:00

test_tilelang_issue_merge_if.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_issue_sm120_tma_smem_alignment.py

fix: TMA alignment to 1024 bytes on Blackwell (#2134)

2026-05-04 00:12:02 +08:00

test_tilelang_issue_tma_no_ws.py

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

test_tilelang_issue_ws_simt_copy_full_producer_extent.py

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00