mirror of
https://github.com/tile-ai/tilelang.git
synced 2026-10-29 07:53:03 +08:00
Lei Wang
0d19e26819
* [Enhancement] Add VectorizeLoop function and update imports for compatibility * [CI][Test] Improve test cases for vectorization and fix typos in parser comments * lint fix * Fix incorrect module reference for VectorizeLoop transformation * Refactor vectorize_loop transformation by removing unused extent mutation logic * [Enhancement] Add support for FP8 data types and global barriers in CUDA codegen * Fix formatting in CUDA FP8 header file for consistency * Refactor CI workflow to use 'tilelang_ci' virtual environment and update CUDA type printing for better clarity * Update submodule 'tvm' to latest commit for improved functionality * Refactor execution backend references from 'dl_pack' to 'dlpack' for consistency and clarity; add apply_simplify function to simplify PrimFunc or IRModule. * Refactor CUDA code for improved readability; clean up formatting and remove unnecessary whitespace in multiple files. * Refactor import statement in test_tilelang_kernel_dequantize_gemm.py to use 'tilelang.language' for consistency * Add CUDA requirements to FP8 test cases and update references for clarity * Add a blank line for improved readability in test_tilelang_kernel_fp8_gemm_mma.py * Fix data type in reference result calculation for consistency in test_tilelang_kernel_gemm_mma_intrinsic.py * Add CUDA requirements and FP8 test cases for matmul and gemv simulations * Remove debug print statements and use tilelang's testing assertion for result validation in test_tilelang_kernel_gemm_mma_intrinsic.py * Remove outdated comment regarding FP8 tests in test_tilelang_kernel_gemv_simt.py * Add BF16 support to matrix multiplication and introduce corresponding test cases * Add a blank line for improved readability in BF16 GEMM test * Update acknowledgements in README to include supervision by Zhi Yang at Peking University
407 lines
13 KiB
Python
407 lines
13 KiB
Python
# Copyright (c) Microsoft Corporation.
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# Licensed under the MIT License.
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import torch
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import torch.backends
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import tilelang
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from tilelang import tvm as tvm
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import tilelang.testing
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import tilelang as TL
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import tilelang.language as T
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from tilelang.intrinsics import (
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make_mma_swizzle_layout as make_swizzle_layout,)
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from tilelang.intrinsics.mma_macro_generator import (
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INT4TensorCoreIntrinEmitter,
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INT4TensorCoreIntrinEmitterWithLadderTransform,
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)
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from tilelang.transform import simplify_prim_func
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tilelang.testing.set_random_seed(0)
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@simplify_prim_func
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def tl_matmul(
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M,
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N,
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K,
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in_dtype,
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out_dtype,
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accum_dtype,
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):
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assert in_dtype in [
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"float16",
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"int8",
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], "Currently only float16 and int8 are supported"
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assert out_dtype in [
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"float16",
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"float32",
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"int32",
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], "Currently only float16, float32 and int32 are supported"
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K = K // 2
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micro_size_x = micro_size_y = micro_size_k = 16
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if accum_dtype == "int32":
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micro_size_k = 32
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# This is a debug config
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block_row_warps = 2
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block_col_warps = 2
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warp_row_tiles = 64
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warp_col_tiles = 64
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chunk = 32 if in_dtype == "float16" else 64
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shared_scope = "shared.dyn"
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# Pipeline Stage
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stage = 2
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block_M = block_row_warps * warp_row_tiles
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block_N = block_col_warps * warp_col_tiles
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block_K = chunk
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A_shape = (M, K) # int8 storage represents int4*2
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B_shape = (N, K) # int8 storage represents int4*2
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A_shared_shape = (block_M, block_K)
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B_shared_shape = (block_N, block_K)
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C_shared_shape = (
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block_M // micro_size_x,
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block_N // micro_size_y,
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micro_size_x,
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micro_size_y,
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)
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warp_size = 32
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threads = warp_size * (block_row_warps * block_col_warps)
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local_size_a = (micro_size_x * micro_size_k) // warp_size
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local_size_b = (micro_size_y * micro_size_k) // warp_size
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local_size_c = (micro_size_x * micro_size_y) // warp_size
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warp_rows = warp_row_tiles // micro_size_x
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warp_cols = warp_col_tiles // micro_size_y
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# MMA Wrapper to Auto Generate Code for MMA
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mma_emitter = INT4TensorCoreIntrinEmitter(
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a_dtype=in_dtype,
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b_dtype=in_dtype,
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accum_dtype=accum_dtype,
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a_transposed=False,
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b_transposed=True,
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block_row_warps=block_row_warps,
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block_col_warps=block_col_warps,
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warp_row_tiles=warp_row_tiles,
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warp_col_tiles=warp_col_tiles,
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chunk=chunk,
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)
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@T.prim_func
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def main(
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A: T.Buffer(A_shape, in_dtype),
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B: T.Buffer(B_shape, in_dtype),
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C: T.Buffer((M, N), out_dtype),
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):
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with T.Kernel(T.ceildiv(N, block_N), T.ceildiv(M, block_M), threads=threads) as (bx, by):
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A_shared = T.alloc_shared(A_shared_shape, in_dtype, scope=shared_scope)
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B_shared = T.alloc_shared(B_shared_shape, in_dtype, scope=shared_scope)
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C_shared = T.alloc_shared(C_shared_shape, out_dtype, scope=shared_scope)
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A_local = T.alloc_local((warp_rows * local_size_a), in_dtype)
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B_local = T.alloc_local((warp_cols * local_size_b), in_dtype)
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C_local = T.alloc_local((warp_rows * warp_cols * local_size_c), accum_dtype)
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thread_binding = T.thread_binding(0, threads, "threadIdx.x")
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T.annotate_layout({
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A_shared: make_swizzle_layout(A_shared),
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B_shared: make_swizzle_layout(B_shared),
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})
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# Improve L2 Cache
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T.use_swizzle(panel_size=10)
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T.clear(C_local)
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for ko in T.Pipelined((K // block_K), num_stages=stage):
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# Load A into shared memory
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for i, k in T.Parallel(block_M, block_K):
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A_shared[i, k] = A[by * block_M + i, ko * block_K + k]
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# Load B into shared memory
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for j, k in T.Parallel(block_N, block_K):
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B_shared[j, k] = B[bx * block_N + j, ko * block_K + k]
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for ki in T.serial(0, (block_K // micro_size_k)):
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# Load A into fragment
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mma_emitter.ldmatrix_a(
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A_local,
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A_shared,
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ki,
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)
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# Load B into fragment
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mma_emitter.ldmatrix_b(
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B_local,
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B_shared,
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ki,
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)
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# Perform Matrix Multiplication
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mma_emitter.mma(A_local, B_local, C_local)
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# Perform STMatrix
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mma_emitter.stmatrix(
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C_local,
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C_shared,
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)
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# Store shared into global
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for i, j in T.Parallel(block_M, block_N):
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C[by * block_M + i, bx * block_N + j] = C_shared[
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i // micro_size_x,
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j // micro_size_y,
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i % micro_size_x,
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j % micro_size_y,
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]
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return main
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def assert_tl_matmul_correctness(M, N, K, in_dtype, out_dtype, accum_dtype):
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matmul = tl_matmul(M, N, K, in_dtype, out_dtype, accum_dtype)
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mod, params = TL.lower(matmul)
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src_code = mod.imported_modules[0].get_source()
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# src_code is the generated cuda source
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assert src_code is not None
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A = torch.randint(0, 4, (M, K), device="cuda", dtype=getattr(torch, in_dtype))
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B = torch.randint(0, 4, (N, K), device="cuda", dtype=getattr(torch, in_dtype))
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C = torch.zeros(M, N, device="cuda", dtype=getattr(torch, accum_dtype))
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compressed_A = (A[:, ::2] & 0x0F) + ((A[:, 1::2] & 0x0F) << 4)
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compressed_B = (B[:, ::2] & 0x0F) + ((B[:, 1::2] & 0x0F) << 4)
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mod = TL.Profiler(mod, params, [], TL.TensorSupplyType.Integer)
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mod(compressed_A, compressed_B, C)
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print(C)
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latency = mod.do_bench(mod.func, warmup=25, profiler="tvm")
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print(latency)
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# Ensure that the latency is not None
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assert latency is not None
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# Get Reference Result
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ref_c = torch.matmul(A.to(torch.float32), B.T.to(torch.float32)).to(getattr(torch, accum_dtype))
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print(ref_c)
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torch.testing.assert_close(C, ref_c, rtol=1e-2, atol=1e-2)
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@simplify_prim_func
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def tl_matmul_weight_only_transform(
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M,
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N,
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K,
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in_dtype,
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out_dtype,
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accum_dtype,
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):
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K = K // 2
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assert in_dtype in [
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"float16",
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"int8",
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], "Currently only float16 and int8 are supported"
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assert out_dtype in [
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"float16",
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"float32",
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"int32",
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], "Currently only float16, float32 and int32 are supported"
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micro_size_x = micro_size_y = micro_size_k = 16
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if out_dtype == "int32":
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micro_size_k = 32
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transform_b = 3
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# This is a debug config
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block_row_warps = 2
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block_col_warps = 2
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warp_row_tiles = 64
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warp_col_tiles = 64
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chunk = 32 if in_dtype == "float16" else 64
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shared_scope = "shared.dyn"
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# Pipeline Stage
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stage = 2
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block_M = block_row_warps * warp_row_tiles
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block_N = block_col_warps * warp_col_tiles
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block_K = chunk
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A_shape = (M, K)
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B_shape = (N // micro_size_y, K // micro_size_k, micro_size_y, micro_size_k)
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A_shared_shape = (
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block_M,
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block_K,
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)
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B_shared_shape = (
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block_N // micro_size_y,
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block_K // micro_size_k,
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micro_size_y,
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micro_size_k,
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)
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C_shared_shape = (
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block_M // micro_size_x,
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block_N // micro_size_y,
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micro_size_x,
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micro_size_y,
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)
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warp_size = 32
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threads = warp_size * (block_row_warps * block_col_warps)
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local_size_a = (micro_size_x * micro_size_k) // warp_size
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local_size_b = (micro_size_y * micro_size_k) // warp_size
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local_size_c = (micro_size_x * micro_size_y) // warp_size
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warp_rows = warp_row_tiles // micro_size_x
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warp_cols = warp_col_tiles // micro_size_y
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# MMA Wrapper to Auto Generate Code for MMA
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mma_emitter = INT4TensorCoreIntrinEmitterWithLadderTransform(
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a_dtype=in_dtype,
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b_dtype=in_dtype,
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accum_dtype=accum_dtype,
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a_transposed=False,
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b_transposed=True,
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block_row_warps=block_row_warps,
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block_col_warps=block_col_warps,
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warp_row_tiles=warp_row_tiles,
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warp_col_tiles=warp_col_tiles,
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chunk=chunk,
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transform_kind_b=transform_b,
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)
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@T.prim_func
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def main(
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A: T.Buffer(A_shape, in_dtype),
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B: T.Buffer(B_shape, in_dtype),
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C: T.Buffer((M, N), out_dtype),
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):
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with T.Kernel(T.ceildiv(N, block_N), T.ceildiv(M, block_M), threads=threads) as (bx, by):
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A_shared = T.alloc_shared(A_shared_shape, in_dtype, scope=shared_scope)
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B_shared = T.alloc_shared(B_shared_shape, in_dtype, scope=shared_scope)
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C_shared = T.alloc_shared(C_shared_shape, out_dtype, scope=shared_scope)
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A_local = T.alloc_local((warp_rows * local_size_a), in_dtype)
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B_local = T.alloc_local((warp_cols * local_size_b), in_dtype)
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C_local = T.alloc_local((warp_rows * warp_cols * local_size_c), accum_dtype)
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thread_binding = T.thread_binding(0, threads, "threadIdx.x")
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T.annotate_layout({
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A_shared: make_swizzle_layout(A_shared),
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B_shared: make_swizzle_layout(B_shared),
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})
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# Improve L2 Cache
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T.use_swizzle(panel_size=10)
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T.clear(C_local)
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for ko in T.Pipelined((K // block_K), num_stages=stage):
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# Load A into shared memory
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for i, k in T.Parallel(block_M, block_K):
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A_shared[i, k] = A[by * block_M + i, ko * block_K + k]
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# Load B into shared memory
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for j, k, jj, kk in T.Parallel(block_N // micro_size_y, block_K // micro_size_k,
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micro_size_y, micro_size_k):
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B_shared[j, k, jj, kk] = B[bx * (block_N // micro_size_y) + j,
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ko * (block_K // micro_size_k) + k, jj, kk]
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for ki in T.serial(0, (block_K // micro_size_k)):
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# Load A into fragment
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mma_emitter.ldmatrix_a(
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A_local,
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A_shared,
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ki,
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)
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# Load B into fragment
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mma_emitter.ldmatrix_b(
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B_local,
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B_shared,
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ki,
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)
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# Perform Matrix Multiplication
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mma_emitter.mma(A_local, B_local, C_local)
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# Perform STMatrix
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mma_emitter.stmatrix(
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C_local,
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C_shared,
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)
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# Store shared into global
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for i, j in T.Parallel(block_M, block_N):
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C[by * block_M + i, bx * block_N + j] = C_shared[
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i // micro_size_x,
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j // micro_size_y,
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i % micro_size_x,
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j % micro_size_y,
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]
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return main
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def assert_tl_matmul_weight_only_transform_correctness(M, N, K, in_dtype, out_dtype, accum_dtype):
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matmul = tl_matmul_weight_only_transform(M, N, K, in_dtype, out_dtype, accum_dtype)
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mod, params = TL.lower(matmul)
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src_code = mod.imported_modules[0].get_source()
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# src_code is the generated cuda source
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assert src_code is not None
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transform_b = 3
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A = torch.randint(0, 4, (M, K), device="cuda", dtype=getattr(torch, in_dtype))
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B = torch.randint(0, 4, (N, K), device="cuda", dtype=getattr(torch, in_dtype))
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C = torch.zeros(M, N, device="cuda", dtype=getattr(torch, accum_dtype))
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compressed_A = (A[:, ::2] & 0x0F) + ((A[:, 1::2] & 0x0F) << 4)
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compressed_B = (B[:, ::2] & 0x0F) + ((B[:, 1::2] & 0x0F) << 4)
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ladder_permutate_config = tilelang.ops.LadderPermutateConfig(
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M=N,
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N=(K // 2),
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datatype="int8",
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storage_dtype="int8",
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transform_kind=transform_b,
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transpose_matrix=True,
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)
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ladder_permutate = tilelang.ops.LadderPermutate(ladder_permutate_config)
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mod = TL.Profiler(mod, params, [], TL.TensorSupplyType.Integer)
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LB = ladder_permutate(compressed_B.cpu()).cuda()
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mod(compressed_A, LB, C)
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latency = mod.do_bench(mod.func, warmup=25)
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print(f"Latency: {latency}")
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# Ensure that the latency is not None
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assert latency is not None
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# Get Reference Result
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ref_c = torch.matmul(A.to(torch.float32), B.T.to(torch.float32)).to(getattr(torch, accum_dtype))
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print(C)
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print(ref_c)
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torch.testing.assert_close(C, ref_c, rtol=1e-2, atol=1e-2)
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@tilelang.testing.requires_package("bitblas")
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def test_assert_tl_matmul_weight_only_transform():
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assert_tl_matmul_weight_only_transform_correctness(128, 128, 128, "int8", "int32", "int32")
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if __name__ == "__main__":
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tilelang.testing.main()
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