Yangye ZhouandLeiWang1999 ac2e1d7918 [BugFix][Transform] Deduplicate DeclBuffer names after loop unrolling (#2290) ...

[BugFix][Transform] Freshen buffer defs after loop unroll

UnrollLoop clones each loop body with Substitute, which preserves Buffer object identity for definitions inside the body. This can define the same DeclBuffer handle in multiple unrolled copies after flattening and violate TIR SSA. Freshen buffer definitions per cloned body while preserving DeclBuffer backing data aliases.

Co-authored-by: LeiWang1999 <leiwang1999@outlook.com>

2026-05-29 01:03:43 +08:00

..

test_nullable_buffer_params.py

[BugFix] ArgBinder: relax shared-shape binding for unused nullable buffers (#1870)

2026-02-24 11:43:55 +08:00

test_readonly_param_const_codegen.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_transform_cluster_planning.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_config_index_bitwidth.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_transform_decouple_type_cast.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_disable_memory_reuse.py

[CUDA][IR] Preserve dynamic shared memory aliases (#2240)

2026-05-21 18:12:58 +08:00

test_tilelang_transform_flatten_buffer.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_fuse_mbarrier_arrive_expect_tx.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_hoist_broadcast_values.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_if_stmt_binding.py

[Transform][Pipeline] Keep pointer binds out of replayable scalar inlining (#2278)

2026-05-26 22:53:27 +08:00

test_tilelang_transform_im2col_fallback.py

[Example] Migrate eligible examples to eager style (#2010)

2026-05-21 20:27:06 +08:00

test_tilelang_transform_inject_fence_proxy.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_inject_set_max_nreg.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_Inject_software_pipeline.py

[Pipeline] Refactor software pipeline transforms (#2245)

2026-05-26 15:55:03 +08:00

test_tilelang_transform_inject_tcgen05_fence.py

[Backend] Promote PassPipeline to backend sub-folder and cleanup Metal Leftover (#2291)

2026-05-28 16:44:10 +08:00

test_tilelang_transform_layout_inference.py

[TIR][Transform] Fix ragged SIMT loop partitioning (#2296)

2026-05-28 19:46:55 +08:00

test_tilelang_transform_legalize_negative_index.py

[Enhancement]Support mixed-sign ramp indices in LegalizeNegativeIndex (#2225)

2026-05-19 18:03:43 +08:00

test_tilelang_transform_legalize_safe_memory_access.py

Fix atomic_load access_ptr lowering for dynamic indices (#2157)

2026-05-25 13:20:47 +08:00

test_tilelang_transform_legalize_vectorized_loop.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_transform_let_inline.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_lexical_alloc_scope.py

[Backend] Promote PassPipeline to backend sub-folder and cleanup Metal Leftover (#2291)

2026-05-28 16:44:10 +08:00

test_tilelang_transform_loop_unswitching.py

[BugFix] LoopUnswitching: gate non-trivial else behind PassConfig (#1816)

2026-02-09 11:20:20 +08:00

test_tilelang_transform_lower_hopper_intrin.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_lower_ldgstg.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_lower_ptx_async_copy.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_lower_shared_barrier.py

[Backend] Promote PassPipeline to backend sub-folder and cleanup Metal Leftover (#2291)

2026-05-28 16:44:10 +08:00

test_tilelang_transform_lower_shared_tmem.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_lower_tile_op.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_make_packed_api.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_pipeline_barrier_ownership.py

[Example] Migrate eligible examples to eager style (#2010)

2026-05-21 20:27:06 +08:00

test_tilelang_transform_pipeline_planning.py

[Pipeline] Refactor software pipeline transforms (#2245)

2026-05-26 15:55:03 +08:00

test_tilelang_transform_plan_update_buffer_allocation_location.py

[Backend] Promote PassPipeline to backend sub-folder and cleanup Metal Leftover (#2291)

2026-05-28 16:44:10 +08:00

test_tilelang_transform_producer_consumer_ws.py

[Transform] Preserve WS prelude liveness ordering (#2233)

2026-05-21 00:41:21 +08:00

test_tilelang_transform_simplify.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_split_host_device.py

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

test_tilelang_transform_thread_sync.py

[TIR][Transform] Fix shared.dyn alias sync analysis (#2293)

2026-05-28 15:36:19 +08:00

test_tilelang_transform_unroll_loop.py

[BugFix][Transform] Deduplicate DeclBuffer names after loop unrolling (#2290)

2026-05-29 01:03:43 +08:00