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Lei Wang 1a10fd8d87 [Language][CUDA] Add T.fma and T.fmul round-to-nearest intrinsics (#3134 )

Introduce two CUDA-specific math intrinsics with guaranteed instruction
selection:

- T.fma(x, y, z): fused multiply-add whose fusion (single rounding) is
  guaranteed regardless of NVCC contraction settings.
- T.fmul(x, y): multiply with an explicit boundary that is never
  contracted into a neighbouring FMA.

Unlike the ieee_* family (which carries an explicit rounding mode and
stays scalar), both ops fix round-to-nearest and are marked
TVectorizable, so T.Parallel loops containing them keep their vectorized
loads/stores:

- scalar: __fmul_rn/__fmaf_rn (fp32), __dmul_rn/__fma_rn (fp64),
  __hmul_rn/__hfma (fp16/bf16)
- vectorized on SM100+: packed x2 helpers tl::mul2/tl::fma2
- vectorized elsewhere: per-lane scalar calls
- CuTeDSL: tl.ieee_fmul/tl.ieee_fmaf with rounding="rn", expanded per
  lane through a register tensor for vector dtypes

The packed x2 pair-decomposition logic is extracted from
PrintVecBinaryOp into a reusable EmitPackedX2Call helper (no behavior
change), alongside a new EmitPerLaneScalarCall fallback.

2026-09-02 16:07:16 +08:00

test_cuda_bfloat16_math_intrinsics.py

[CUDA] Reduce template include overhead (#2474 )

2026-07-01 16:53:07 +08:00

test_cuda_f32x2_intrinsics.py

[CUDA][Reduce] Add PassConfig for FP32x2 accumulation (#3128 )

2026-09-02 01:43:37 +08:00

test_cuda_fma_fmul.py

[Language][CUDA] Add T.fma and T.fmul round-to-nearest intrinsics (#3134 )

2026-09-02 16:07:16 +08:00

test_cuda_mma_sm75_dispatch.py

[CUDA] Extend the GEMM FMA fallback to SM75 (#2811 )