Chennes 9f76d522ed [BugFix] Fix vectorized atomic_add dtype mismatch reinterpret (#2414) ...

Vectorized atomic_add into an fp16/bf16 destination with an fp32 source
bit-reinterpreted the source float2 as half2/__nv_bfloat162 instead of
numerically converting it, silently producing wrong results. This hit
both the auto-vectorized T.atomic_add path (AtomicAddx2 value form) and
the explicit T.atomic_addx2 API (pointer form).

Add float2 / float* converting overloads (round-to-nearest) to ToHalf2
and ToBfloat162 so the vectorized helper converts instead of
reinterpreting the source bytes. Add mixed-dtype regression tests for
both entry points.

Fixes #2382

2026-06-19 23:21:35 +08:00

..

amd

[Backend] Add target detector/normalizer registeration and merge ExecutionBackend into backend module (#2323)

2026-06-09 00:35:07 +08:00

analysis

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

arith

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

autotune

[CuTeDSL] Integrate host codegen call sites (#2221)

2026-05-21 20:28:41 +08:00

cache

[JIT] Remove frontend disk cache (#2363)

2026-06-10 00:05:22 +08:00

carver

[BugFix] Fix IntrinInfo repr (#2175)

2026-05-22 16:16:50 +08:00

components

Fix storage rewrite source codegen test (#2353)

2026-06-10 15:17:45 +08:00

cpu

[Transform] Materialize kernel launch per backend (#2387)

2026-06-12 17:14:02 +08:00

cuda

[BugFix] Fix bf16 CUDA exp self-recursion (#2402)

2026-06-15 21:21:32 +08:00

debug

[feat] add pass diff show for debugging (#2375)

2026-06-16 19:38:22 +08:00

fastmath

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

issue

[Backend] Cleanup Metal Codegen, split AsyncCopy lowering and common target utils (#2361)

2026-06-09 20:20:25 +08:00

jit

[BugFix][CuTeDSL] Fix TileKernels scan, optional-shape, and e5m6 paths (#2369)

2026-06-17 13:41:26 +08:00

kernel

[Backend] Support TMA lowering for arbitrary (swizzled) SMEM layout (#2380)

2026-06-18 18:42:01 +08:00

language

[BugFix] Fix vectorized atomic_add dtype mismatch reinterpret (#2414)

2026-06-19 23:21:35 +08:00

layout

[Backend] Support TMA lowering for arbitrary (swizzled) SMEM layout (#2380)

2026-06-18 18:42:01 +08:00

llvm

[Feature] Add LLVM backend support (#2409)

2026-06-18 15:25:03 +08:00

math

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

metal

[Metal] Add Metal GEMM support with simdgroup_matrix MMA (#1869)

2026-05-22 12:30:54 +08:00

profiler

[tilelang] Fix CUPTI cache flush filtering (#2244)

2026-05-22 16:15:53 +08:00

runtime

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

target

[BugFix][CuTeDSL] Fix TileKernels scan, optional-shape, and e5m6 paths (#2369)

2026-06-17 13:41:26 +08:00

tilelibrary

[Backend] Refactor gemm_sp (#2048)

2026-05-19 13:33:41 +08:00

transform

[CUDA] Align swizzled TMA shared buffers (#2391)

2026-06-15 01:42:06 +08:00

utils

[BugFix] Fix sparse int8 default metadata dtype (#2229)

2026-05-21 11:05:10 +08:00

webgpu

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_version_provider.py

[Build] Fix sdist version metadata (#2374)

2026-06-11 20:40:16 +08:00