qutaoandClaude Fable 5 9c673b5e0c Add T.copy_ue4m3_scale_tile scale staging helper ...

The example and the maint warp-specialized benchmark each carried a
private macro with the blockscaled_chunk_kmajor tile addressing spelled
out by hand. Move that knowledge into the library next to
T.mma_gemm_blockscaled:

- T.ue4m3_scale_tile_source_coords: the single source of the packed
  scale tile addressing (tiles are contiguous in this layout);
  words_per_kblock stays a parameter so future contracts
  (block_K != 256, MX scale packings) reuse it.
- T.copy_ue4m3_scale_tile: cooperative whole-block staging macro with
  trace-time dtype/shape validation, used by the example. The scale
  operand stays visible in user kernels; only the layout math is hidden.

The maint kernel keeps its producer-warp-group staging schedule and
reuses the coords helper. Validated: nvf4 language + example CLI tests
(91 passed incl. a new validation test), example and WS benchmark
--verify pass.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

2026-07-10 14:28:25 +08:00

..

amd

[Backend] Add target detector/normalizer registeration and merge ExecutionBackend into backend module (#2323)

2026-06-09 00:35:07 +08:00

analysis

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

arith

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

autotune

[CuTeDSL] Integrate host codegen call sites (#2221)

2026-05-21 20:28:41 +08:00

cache

[CUDA][Cache] Include compile options in binary cache key (#2532)

2026-07-07 00:09:22 +08:00

carver

[BugFix] Fix IntrinInfo repr (#2175)

2026-05-22 16:16:50 +08:00

components

Fix storage rewrite source codegen test (#2353)

2026-06-10 15:17:45 +08:00

cpu

[Transform] Materialize kernel launch per backend (#2387)

2026-06-12 17:14:02 +08:00

cuda

[CUDA] Reduce template include overhead (#2474)

2026-07-01 16:53:07 +08:00

debug

[Feature][Tool] Add pass_visualizer: structure-tree pass browser (#2449)

2026-07-06 15:39:54 +08:00

fastmath

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

issue

[BugFix] Sign-extend packed uint32 signed decode (#2500)

2026-07-02 13:12:56 +08:00

jit

[CUDA] Add target code attribute support (#2454)

2026-06-25 16:49:20 +08:00

kernel

[Backend] Support TMA lowering for arbitrary (swizzled) SMEM layout (#2380)

2026-06-18 18:42:01 +08:00

language

Add T.copy_ue4m3_scale_tile scale staging helper

2026-07-10 14:28:25 +08:00

layout

[Transform][Layout] Avoid thread-indexed replicated fragment readback (#2514)

2026-07-03 14:52:24 +08:00

llvm

[BugFix] Fix llvm auto backend resolution (#2519)

2026-07-06 10:55:13 +08:00

math

[Feature] Expose multiple CUDA intrinsics (#2473)

2026-07-02 17:29:54 +08:00

metal

[BugFix] Fix packed vector type printing for bfloat16 with metal codegen (#2437)

2026-06-23 13:32:11 +08:00

profiler

[tilelang] Fix CUPTI cache flush filtering (#2244)

2026-05-22 16:15:53 +08:00

quantize

Pin scale layout byte-compat with CuTeDSL blocked SF layout

2026-07-10 14:02:15 +08:00

runtime

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

target

[Env] Require JSON for default target config (#2491)

2026-06-30 13:27:34 +08:00

tilelibrary

[Backend] Refactor gemm_sp (#2048)

2026-05-19 13:33:41 +08:00

transform

[TIR][Codegen] Preserve decoupled cast buffer scope (#2545)

2026-07-08 14:36:12 +08:00

utils

[BugFix] Fix sparse int8 default metadata dtype (#2229)

2026-05-21 11:05:10 +08:00

webgpu

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_version_provider.py

[Build] Fix sdist version metadata (#2374)

2026-06-11 20:40:16 +08:00