tilelang

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T

morluto eb2136dae7 [BugFix][ROCm] Lower vector Select conditions lane-wise (#2889 )

#2843 fixed vectorized `T.Select` in the CUDA codegen but the equivalent handling
never landed for HIP, so on gfx942 a vector condition fell through to a scalar
ternary and failed to compile:

    error: value of type 'ushort4' (aka 'HIP_vector_type<unsigned short, 4>')
           is not contextually convertible to 'bool'

Lower vector Select conditions lane-wise instead, scalarizing the expression tree
per lane so branch loads stay inside the ternary rather than being materialized.
Also adds fp8/fp4 handling to PrintVecElemLoad/PrintVecElemStore, which the new
path exercises.

Verified on the gfx942 runner: 1910 passed, 1237 skipped, 0 failed. First fully
clean ROCm leg since CI was re-enabled in #2874.

Known follow-up: vector `builtin::reinterpret` is not scalarized before lane
extraction. A limitation of the new path rather than a regression, tracked
separately.

2026-08-06 20:40:18 -07:00

test_mfma_dtype_str_bug.py

[BugFix] Fix MFMA DataType args causing compilation failure on ROCm (#2726 )

2026-07-22 16:28:11 +08:00

test_tilelang_ds_read_tr.py

[BugFix] Fix ROCm intrinsic resolution after language dialect refactor (#2779 )

2026-07-27 17:58:18 +08:00

test_tilelang_gemm_mfma_intrinsic.py

[Backend] Add target detector/normalizer registeration and merge ExecutionBackend into backend module (#2323 )

2026-06-09 00:35:07 +08:00

test_tilelang_gemm_mfma_preshuffle.py

[Backend] Add target detector/normalizer registeration and merge ExecutionBackend into backend module (#2323 )