Lei Wang 8fd83e22fd [JIT] Remove frontend disk cache (#2363) ...

Remove frontend disk cache

2026-06-10 00:05:22 +08:00

..

amd

[Backend] Add target detector/normalizer registeration and merge ExecutionBackend into backend module (#2323)

2026-06-09 00:35:07 +08:00

analysis

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

arith

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

autotune

[CuTeDSL] Integrate host codegen call sites (#2221)

2026-05-21 20:28:41 +08:00

cache

[JIT] Remove frontend disk cache (#2363)

2026-06-10 00:05:22 +08:00

carver

[BugFix] Fix IntrinInfo repr (#2175)

2026-05-22 16:16:50 +08:00

components

[Runtime][Cache] Make tmp dir default follow cache dir (#2321)

2026-06-02 22:47:36 +08:00

cpu

[Transform] Fix CPU while fallback thread lowering (#2227)

2026-05-20 11:41:45 +08:00

cuda

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

debug

[Backend] Add target detector/normalizer registeration and merge ExecutionBackend into backend module (#2323)

2026-06-09 00:35:07 +08:00

fastmath

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

issue

[Backend] Cleanup Metal Codegen, split AsyncCopy lowering and common target utils (#2361)

2026-06-09 20:20:25 +08:00

jit

[JIT] Improve lazy kernel lookup caching (#2357)

2026-06-09 13:56:03 +08:00

kernel

[Feature] Introduce T.tfloat32 data type support (#2032)

2026-05-21 16:11:32 +08:00

language

[Backend] Add target detector/normalizer registeration and merge ExecutionBackend into backend module (#2323)

2026-06-09 00:35:07 +08:00

layout

[Transform] Respect fragment write owner layouts (#2349)

2026-06-08 00:04:46 +08:00

math

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

metal

[Metal] Add Metal GEMM support with simdgroup_matrix MMA (#1869)

2026-05-22 12:30:54 +08:00

profiler

[tilelang] Fix CUPTI cache flush filtering (#2244)

2026-05-22 16:15:53 +08:00

runtime

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

target

[Backend] Add target detector/normalizer registeration and merge ExecutionBackend into backend module (#2323)

2026-06-09 00:35:07 +08:00

tilelibrary

[Backend] Refactor gemm_sp (#2048)

2026-05-19 13:33:41 +08:00

transform

[Backend] Cleanup Metal Codegen, split AsyncCopy lowering and common target utils (#2361)

2026-06-09 20:20:25 +08:00

utils

[BugFix] Fix sparse int8 default metadata dtype (#2229)

2026-05-21 11:05:10 +08:00

webgpu

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00