qutaoandClaude Fable 5 790a3f0ed1 Support M or N tail tiles in the SM120 NVFP4 example ...

Production shapes rarely keep M (batch x seq) a multiple of 128. Lift
the divisibility requirements to the validated envelope:

- scale packers zero-pad rows to full 128-row tiles (the same ceil
  convention CUTLASS/cuBLAS/CuTeDSL use for the blocked SF tensor), so
  the packed source always has ceil(rows/128)*128 rows;
- the example accepts an arbitrary M or an N tail: TMA loads zero-fill
  out-of-bounds rows and the C store is predicated. N keeps the
  16-byte-aligned-rows rule (N % 8 == 0), the same contiguous-dim
  alignment CuTeDSL validates;
- simultaneous M and N tails are rejected with a clear error: the
  fragment-to-global copy lowering emits the column guard bound from
  the wrong dimension in that case (upstream bug, tracked separately).

Tests: tail-shape runtime correctness (257x384, 130x128, 128x136 with
exact binary-scale references), rejection paths, and packer padding
round-trip.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

2026-07-10 15:07:03 +08:00

..

amd

[Backend] Add target detector/normalizer registeration and merge ExecutionBackend into backend module (#2323)

2026-06-09 00:35:07 +08:00

analysis

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

arith

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

autotune

[CuTeDSL] Integrate host codegen call sites (#2221)

2026-05-21 20:28:41 +08:00

cache

[CUDA][Cache] Include compile options in binary cache key (#2532)

2026-07-07 00:09:22 +08:00

carver

[BugFix] Fix IntrinInfo repr (#2175)

2026-05-22 16:16:50 +08:00

components

Fix storage rewrite source codegen test (#2353)

2026-06-10 15:17:45 +08:00

cpu

[Transform] Materialize kernel launch per backend (#2387)

2026-06-12 17:14:02 +08:00

cuda

[CUDA] Reduce template include overhead (#2474)

2026-07-01 16:53:07 +08:00

debug

[Feature][Tool] Add pass_visualizer: structure-tree pass browser (#2449)

2026-07-06 15:39:54 +08:00

fastmath

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

issue

[BugFix] Sign-extend packed uint32 signed decode (#2500)

2026-07-02 13:12:56 +08:00

jit

[CUDA] Add target code attribute support (#2454)

2026-06-25 16:49:20 +08:00

kernel

[Backend] Support TMA lowering for arbitrary (swizzled) SMEM layout (#2380)

2026-06-18 18:42:01 +08:00

language

Support M or N tail tiles in the SM120 NVFP4 example

2026-07-10 15:07:03 +08:00

layout

[Transform][Layout] Avoid thread-indexed replicated fragment readback (#2514)

2026-07-03 14:52:24 +08:00

llvm

[BugFix] Fix llvm auto backend resolution (#2519)

2026-07-06 10:55:13 +08:00

math

[Feature] Expose multiple CUDA intrinsics (#2473)

2026-07-02 17:29:54 +08:00

metal

[BugFix] Fix packed vector type printing for bfloat16 with metal codegen (#2437)

2026-06-23 13:32:11 +08:00

profiler

[tilelang] Fix CUPTI cache flush filtering (#2244)

2026-05-22 16:15:53 +08:00

quantize

Support M or N tail tiles in the SM120 NVFP4 example

2026-07-10 15:07:03 +08:00

runtime

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

target

[Env] Require JSON for default target config (#2491)

2026-06-30 13:27:34 +08:00

tilelibrary

[Backend] Refactor gemm_sp (#2048)

2026-05-19 13:33:41 +08:00

transform

[TIR][Codegen] Preserve decoupled cast buffer scope (#2545)

2026-07-08 14:36:12 +08:00

utils

[BugFix] Fix sparse int8 default metadata dtype (#2229)

2026-05-21 11:05:10 +08:00

webgpu

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_version_provider.py

[Build] Fix sdist version metadata (#2374)

2026-06-11 20:40:16 +08:00