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tilelang/testing/python/language
Chennes 4f442a395e [BugFix] Reject invalid atomic load and store memory orders (#2666)
T.atomic_load and T.atomic_store previously accepted every order in the shared memory-order map, including operation-illegal combinations that trigger device-side assertions in libcu++.

Validate memory orders against operation-specific allow lists before lowering, report invalid values with a frontend ValueError, and update the documentation and regression coverage accordingly.

Fixes #2574
2026-07-16 14:22:20 +08:00
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