mirror of
https://github.com/tile-ai/tilelang.git
synced 2026-10-21 06:40:23 +08:00
Yongqi Zhuo
4d1503179f
Aliasing buffers must induce the same storage-bit map, bit(k) = flat_output(k) * elem_bits: layout outputs are measured in the buffer's own elements, so a reinterpreting view needs unit conversion on the last (stride-1) output mode, which the generic flat-index reshape cannot express (it drops the position inside a storage slot). TryReinterpretReshape implements the rule uniformly for every element width, replacing the packed-sub-byte special case: - Narrowing by f: old element q becomes new elements f*q .. f*q+f-1, always representable as last_output * f + lane. The sub-byte lane-append/collapse forms are deleted: the trailing lane mode was only ever a legality certificate for the widening direction. - Widening by f: representable only when every aligned group of f old elements sits contiguously in one aligned slot, now proven per reshape (plus thread-mapping invariance for fragments); layouts that interleave storage below the new element width are a hard error instead of silently miscompiling.