Jayce Suanddingsg 39ade83ff2 [BugFix][CUDA] Use PTX v4 atomics for fp16/bf16 atomic_addx4 (#2492) ...

Use PTX v4 atomics for 16-bit CUDA atomic_addx4

The initial fp16/bf16 atomic_addx4 fix avoided the generic float4 path by splitting each operation into two AtomicAddx2 calls. That fixed correctness, but it still used the simulated implementation on Hopper where PTX provides native vector atomics.

Add sm90+ half_t and bfloat16_t AtomicAddx4 overloads backed by the PTX vector forms atom.global.v4.f16.add.noftz and atom.global.v4.bf16.add.noftz, including the existing memory-order variants. Keep the x2 fallback for pre-sm90 targets because PTX vector f16/bf16 atomics require sm90 or newer.

Keep the CUDA language regression focused on fp16/bf16 atomic_addx4 codegen and offset coverage.

Co-authored-by: dingsg <shengge.ding@enflame-tech.com>

2026-07-02 16:21:02 +08:00

..

amd

[Backend] Add target detector/normalizer registeration and merge ExecutionBackend into backend module (#2323)

2026-06-09 00:35:07 +08:00

analysis

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

arith

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

autotune

[CuTeDSL] Integrate host codegen call sites (#2221)

2026-05-21 20:28:41 +08:00

cache

[CUDA][JIT][Cache] Add cross-host CUDA binary cache (#2459)

2026-06-26 15:56:04 +08:00

carver

[BugFix] Fix IntrinInfo repr (#2175)

2026-05-22 16:16:50 +08:00

components

Fix storage rewrite source codegen test (#2353)

2026-06-10 15:17:45 +08:00

cpu

[Transform] Materialize kernel launch per backend (#2387)

2026-06-12 17:14:02 +08:00

cuda

[CUDA] Reduce template include overhead (#2474)

2026-07-01 16:53:07 +08:00

debug

[feat] add pass diff show for debugging (#2375)

2026-06-16 19:38:22 +08:00

fastmath

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

issue

[BugFix] Sign-extend packed uint32 signed decode (#2500)

2026-07-02 13:12:56 +08:00

jit

[CUDA] Add target code attribute support (#2454)

2026-06-25 16:49:20 +08:00

kernel

[Backend] Support TMA lowering for arbitrary (swizzled) SMEM layout (#2380)

2026-06-18 18:42:01 +08:00

language

[BugFix][CUDA] Use PTX v4 atomics for fp16/bf16 atomic_addx4 (#2492)

2026-07-02 16:21:02 +08:00

layout

[Backend] [CUDA] Support GMMA/UMMA lowering for sliced SMEM layout (actually arbitrary layout) (#2452)

2026-07-01 18:21:53 +08:00

llvm

[Feature] Add LLVM backend support (#2409)

2026-06-18 15:25:03 +08:00

math

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

metal

[BugFix] Fix packed vector type printing for bfloat16 with metal codegen (#2437)

2026-06-23 13:32:11 +08:00

profiler

[tilelang] Fix CUPTI cache flush filtering (#2244)

2026-05-22 16:15:53 +08:00

runtime

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

target

[Env] Require JSON for default target config (#2491)

2026-06-30 13:27:34 +08:00

tilelibrary

[Backend] Refactor gemm_sp (#2048)

2026-05-19 13:33:41 +08:00

transform

[Pipeline] Fix physical async wait counts (#2505)

2026-07-02 15:08:39 +08:00

utils

[BugFix] Fix sparse int8 default metadata dtype (#2229)

2026-05-21 11:05:10 +08:00

webgpu

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_version_provider.py

[Build] Fix sdist version metadata (#2374)

2026-06-11 20:40:16 +08:00