xiaoyouPREG ffeda9f394 [BugFix] Pack 32-lane 8-bit CUDA vectors correctly (#2701) ...

* [BugFix] Pack 32-lane 8-bit CUDA vectors correctly

* [Test] Avoid SM100-only store in int8 broadcast regression

* [BugFix] Move int8x32 packing into CUDA templates

2026-07-21 13:36:03 +08:00

..

test_tilelang_bf16x2_pack_special_values.py

[BugFix] Preserve bf16 NaN and Inf during RNE packing (#2690)

2026-07-17 13:50:39 +08:00

test_tilelang_issue_96.py

[Bugfix] Open Rocm ci test and fix some bugs. (#1443)

2026-01-06 02:18:29 +08:00

test_tilelang_issue_814.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_issue_830.py

[Bugfix] Open Rocm ci test and fix some bugs. (#1443)

2026-01-06 02:18:29 +08:00

test_tilelang_issue_1001.py

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

test_tilelang_issue_1008.py

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

test_tilelang_issue_1026.py

[Feature] Reimplement Threadsync with ConstrVisitor (#1631)

2026-01-15 18:59:50 +08:00

test_tilelang_issue_1115.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_issue_1198.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_issue_1210.py

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

test_tilelang_issue_1237.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_issue_1257.py

[Refactor] Introduce T.access_of to combine T.address_of and access_ptr (#1827)

2026-02-11 22:51:59 +08:00

test_tilelang_issue_1263.py

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

test_tilelang_issue_1374.py

[Feat] Add strong checker to detect data racing in T.Parallel (#1615)

2026-01-06 17:31:24 +08:00

test_tilelang_issue_1549.py

[Refactor] Unify @jit and @lazy_jit into a single @jit decorator (#1632)

2026-01-09 15:41:39 +08:00

test_tilelang_issue_1601.py

[Refactor] Unify @jit and @lazy_jit into a single @jit decorator (#1632)

2026-01-09 15:41:39 +08:00

test_tilelang_issue_1604.py

[Feature] Reimplement Threadsync with ConstrVisitor (#1631)

2026-01-15 18:59:50 +08:00

test_tilelang_issue_1678.py

[Bugfix][Refactor] Always disable light storage reuse (#1691)

2026-01-19 18:06:35 +08:00

test_tilelang_issue_1690.py

[EagerJIT] Lazy Evaluation of Kernel Body in Eager JIT (#1690) (#1694)

2026-01-23 14:33:12 +08:00

test_tilelang_issue_1697.py

[BugFix] Stride check and fix for tensors with zero-stride argument (#1749)

2026-01-29 23:59:24 +08:00

test_tilelang_issue_1719.py

[Layout] Fix Layout Bugs in Parallel and Reduce (#1713)

2026-01-28 10:56:25 +08:00

test_tilelang_issue_1728.py

[BugFix] Remove unnecessary binding in loop variable analysis and add test for issue 1728 (#1735)

2026-01-27 14:43:28 +08:00

test_tilelang_issue_1734.py

[Feature] Support Pass LoopUnswitching (#1747)

2026-02-01 00:32:51 +08:00

test_tilelang_issue_1744.py

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

test_tilelang_issue_1810.py

[BugFix] Fix fp16 annotate_l2_hit_ratio host stub compilation (issue #1810) (#1818)

2026-02-09 13:26:17 +08:00

test_tilelang_issue_1846.py

[BugFix] Fix eager mode where there is no tensor args (#1851)

2026-02-16 00:34:10 +08:00

test_tilelang_issue_1993.py

[Bugfix] Raise error on zero grid dimension instead of silent clamp (#1994)

2026-03-30 16:14:35 +08:00

test_tilelang_issue_2123.py

[Backend] Promote PassPipeline to backend sub-folder and cleanup Metal Leftover (#2291)

2026-05-28 16:44:10 +08:00

test_tilelang_issue_2188.py

[Feature] Support named barrier arrive (#2194)

2026-05-26 12:57:52 +08:00

test_tilelang_issue_2292.py

[BugFix] Fix eager JIT sub-btye shape binding (#2334)

2026-06-05 13:53:12 +08:00

test_tilelang_issue_2307.py

[TIR][Transform] Partition parallel loops with fragment access (#2340)

2026-06-05 14:37:46 +08:00

test_tilelang_issue_2365.py

[Pipeline] Simplify async copy lowering (#2444)

2026-06-24 15:11:05 +08:00

test_tilelang_issue_2433.py

[BugFix] Fix T.Persistent dropping tiles when last dim is not a multiple of group_size (#2455)

2026-06-26 14:12:53 +08:00

test_tilelang_issue_2480.py

[BugFix] Pack 32-lane 8-bit CUDA vectors correctly (#2701)

2026-07-21 13:36:03 +08:00

test_tilelang_issue_2522.py

[BugFix] Fix WGMMA C-store layout for multiple warpgroups along M (#2663)

2026-07-17 17:09:22 +08:00

test_tilelang_issue_2529.py

[BugFix] Prevent partial 1-D TMA stores from bypassing bounds checks (#2716)

2026-07-20 19:42:49 +08:00

test_tilelang_issue_2554.py

[BugFix] Support runtime-dependent vector negative indices (#2654)

2026-07-16 18:30:46 +08:00

test_tilelang_issue_2600.py

[BugFix] Reject invalid dtypes in T.dp4a (#2652)

2026-07-13 17:13:24 +08:00

test_tilelang_issue_merge_if.py

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_tilelang_issue_serial_fragment_access.py

[BugFix] Improve diagnostic for T.serial fragment access (#2462)

2026-06-28 13:05:51 +08:00

test_tilelang_issue_sm120_tma_smem_alignment.py

[Backend] Cleanup Metal Codegen, split AsyncCopy lowering and common target utils (#2361)

2026-06-09 20:20:25 +08:00

test_tilelang_issue_tma_no_ws.py

[Transform] Place auto WS producers in first warp group (#2315)

2026-06-04 14:47:52 +08:00

test_tilelang_issue_ws_simt_copy_full_producer_extent.py

[Transform] Place auto WS producers in first warp group (#2315)

2026-06-04 14:47:52 +08:00

test_tilelang_u32_signed_decode.py

[BugFix] Sign-extend packed uint32 signed decode (#2500)

2026-07-02 13:12:56 +08:00