Lei Wang 23d2f25673 [CUDA] Add target code attribute support (#2454) ...

* Add CUDA target code attr support

* Add CUDA target normalization support

Introduced a new function to normalize CUDA targets, ensuring that the target is correctly identified and transformed based on the detected architecture. Added a test to verify that the bare CUDA target uses the detected architecture accurately.

2026-06-25 16:49:20 +08:00

..

amd

[Backend] Add target detector/normalizer registeration and merge ExecutionBackend into backend module (#2323)

2026-06-09 00:35:07 +08:00

analysis

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

arith

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

autotune

[CuTeDSL] Integrate host codegen call sites (#2221)

2026-05-21 20:28:41 +08:00

cache

[JIT] Remove frontend disk cache (#2363)

2026-06-10 00:05:22 +08:00

carver

[BugFix] Fix IntrinInfo repr (#2175)

2026-05-22 16:16:50 +08:00

components

Fix storage rewrite source codegen test (#2353)

2026-06-10 15:17:45 +08:00

cpu

[Transform] Materialize kernel launch per backend (#2387)

2026-06-12 17:14:02 +08:00

cuda

[BugFix] Fix bf16 CUDA exp self-recursion (#2402)

2026-06-15 21:21:32 +08:00

debug

[feat] add pass diff show for debugging (#2375)

2026-06-16 19:38:22 +08:00

fastmath

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

issue

[Pipeline] Simplify async copy lowering (#2444)

2026-06-24 15:11:05 +08:00

jit

[CUDA] Add target code attribute support (#2454)

2026-06-25 16:49:20 +08:00

kernel

[Backend] Support TMA lowering for arbitrary (swizzled) SMEM layout (#2380)

2026-06-18 18:42:01 +08:00

language

[BugFix] Fix make_int sign-extending negative int8 lanes (#2438)

2026-06-23 14:40:11 +08:00

layout

[Backend] Support TMA lowering for arbitrary (swizzled) SMEM layout (#2380)

2026-06-18 18:42:01 +08:00

llvm

[Feature] Add LLVM backend support (#2409)

2026-06-18 15:25:03 +08:00

math

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

metal

[BugFix] Fix packed vector type printing for bfloat16 with metal codegen (#2437)

2026-06-23 13:32:11 +08:00

profiler

[tilelang] Fix CUPTI cache flush filtering (#2244)

2026-05-22 16:15:53 +08:00

runtime

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

target

[CUDA] Add target code attribute support (#2454)

2026-06-25 16:49:20 +08:00

tilelibrary

[Backend] Refactor gemm_sp (#2048)

2026-05-19 13:33:41 +08:00

transform

[Pipeline] Simplify async copy lowering (#2444)

2026-06-24 15:11:05 +08:00

utils

[BugFix] Fix sparse int8 default metadata dtype (#2229)

2026-05-21 11:05:10 +08:00

webgpu

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00

test_version_provider.py

[Build] Fix sdist version metadata (#2374)

2026-06-11 20:40:16 +08:00