Kashif Rasul 1abf2f906b Scalarize vectorized math intrinsics on HIP (#2286) ...

* Scalarize vector math intrinsics for HIP codegen

* Clarify HIP fp32 vector-math comment in scalarizer

* fix comment

* Scalarize HIP vector math via PrintCallExtern, not generic Shuffle

The generic Shuffle re-pack emits one ctor arg per logical lane, which is
wrong for HIP packed carrier types (float32x8->ulonglong4, float16x4->uint2).
Emit a vector call_pure_extern with the element-derived extern name instead
and let CodeGenTileLangHIP::PrintCallExtern store each lane (PrintVecElemStore),
which is carrier-aware.

* Add HIP vector math scalarizer test

* JIT-decorate scalarizer test helper

2026-06-01 13:33:18 +08:00

..

amd

Scalarize vectorized math intrinsics on HIP (#2286)

2026-06-01 13:33:18 +08:00

analysis

[Refactor][Pipeline] Run pipeline rewriting before layout inference and stabilize tiled WS (#2002)

2026-04-07 23:54:55 +08:00

arith

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

autotune

[CuTeDSL] Integrate host codegen call sites (#2221)

2026-05-21 20:28:41 +08:00

cache

Optimize disk cache source loading (#2176)

2026-05-25 15:49:36 +08:00

carver

[BugFix] Fix IntrinInfo repr (#2175)

2026-05-22 16:16:50 +08:00

components

[CUDA][IR] Preserve dynamic shared memory aliases (#2240)

2026-05-21 18:12:58 +08:00

cpu

[Transform] Fix CPU while fallback thread lowering (#2227)

2026-05-20 11:41:45 +08:00

cuda

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

debug

[CUDA] Improve int4 GEMM lowering and packed codegen support (#2073)

2026-04-22 00:09:01 +08:00

fastmath

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

issue

[Backend] Promote PassPipeline to backend sub-folder and cleanup Metal Leftover (#2291)

2026-05-28 16:44:10 +08:00

jit

[CuTeDSL] Integrate host codegen call sites (#2221)

2026-05-21 20:28:41 +08:00

kernel

[Feature] Introduce T.tfloat32 data type support (#2032)

2026-05-21 16:11:32 +08:00

language

[Feature] Add read option to TMA store wait (#2300)

2026-05-31 03:51:36 +08:00

layout

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

math

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

metal

[Metal] Add Metal GEMM support with simdgroup_matrix MMA (#1869)

2026-05-22 12:30:54 +08:00

profiler

[tilelang] Fix CUPTI cache flush filtering (#2244)

2026-05-22 16:15:53 +08:00

runtime

[TIR][IR] Update to use tirx (#2216)

2026-05-20 15:38:13 +08:00

target

[TileOP] Add scan operators (#2262)

2026-05-25 17:41:10 +08:00

tilelibrary

[Backend] Refactor gemm_sp (#2048)

2026-05-19 13:33:41 +08:00

transform

[Transform] Reduce ragged SIMT copy padding (#2302)

2026-05-29 14:24:49 +08:00

utils

[BugFix] Fix sparse int8 default metadata dtype (#2229)

2026-05-21 11:05:10 +08:00

webgpu

[Enhancement] Update examples and tests for improved type handling functionality (#1448)

2025-12-17 14:41:25 +08:00